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1. 发明授权

US09070773B2 Semiconductor device including a thin film transistor and a capacitor 有权
标题翻译：包括薄膜晶体管和电容器的半导体器件
公开(公告)号：US09070773B2
公开(公告)日：2015-06-30
申请号：US13756783
申请日：2013-02-01
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Akira Ishikawa
IPC分类号： H01L29/786 , G02F1/1362 , H01L27/12 , H01L29/49
CPC分类号： H01L29/786 , G02F1/136213 , H01L27/124 , H01L27/1248 , H01L27/1255 , H01L29/4908 , H01L29/78648 , Y10S257/903 , Y10S257/906 , Y10S257/908 , Y10S257/924
摘要： A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a drain electrode in a semiconductor device having a thin film transistor and a holding capacitance with three or more capacitance electrodes is provided. Before forming the source electrode and the drain electrode, a crystalline silicon film for relaxing the stress is formed, then a contact hole connecting to the semiconductor film of the thin film transistor is opened, and a metal film to be the source electrode and the drain electrode is formed.
摘要翻译：在具有薄膜晶体管和保持电容的半导体器件中形成源电极和漏电极时由于应力引起的半导体膜，电容电极等的裂纹的半导体器件及其制造方法提供三个或更多个电容电极。在形成源电极和漏电极之前，形成用于缓和应力的晶体硅膜，然后打开与薄膜晶体管的半导体膜连接的接触孔，并将作为源电极和漏极的金属膜形成电极。

2. 发明授权

US09041154B2 Contact structure and semiconductor memory device using the same 有权
标题翻译：接触结构和使用其的半导体存储器件
公开(公告)号：US09041154B2
公开(公告)日：2015-05-26
申请号：US13786463
申请日：2013-03-06
申请人： NANYA TECHNOLOGY CORP.
发明人： Chien-An Yu , Chih-Huang Wu
IPC分类号： H01L29/00 , H01L27/04 , H01L23/522 , H01L27/06 , H01L27/108 , H01L49/02
CPC分类号： H01L27/04 , H01L23/5223 , H01L27/0629 , H01L27/10852 , H01L27/10876 , H01L27/10888 , H01L27/10894 , H01L28/40 , H01L28/60 , H01L28/91 , H01L2924/0002 , Y10S257/906 , H01L2924/00
摘要： A semiconductor memory device includes a substrate having thereon a memory array region and a periphery circuit region. A first dielectric layer covers the memory array region and the periphery circuit region on the substrate. A second dielectric layer covers the memory array region and the periphery circuit region on the first dielectric layer. At least a capacitor structure is provided in the memory array region. The capacitor structure includes an electrode material layer embedded in the second dielectric layer. The semiconductor memory device further includes a contact structure comprising the electrode material layer.
摘要翻译：半导体存储器件包括其上具有存储器阵列区域和外围电路区域的衬底。第一电介质层覆盖衬底上的存储器阵列区域和外围电路区域。第二电介质层覆盖第一电介质层上的存储器阵列区域和外围电路区域。在存储器阵列区域中至少提供一个电容器结构。电容器结构包括嵌入在第二电介质层中的电极材料层。半导体存储器件还包括包括电极材料层的接触结构。

3. 发明授权

US08643021B2 Semiconductor device including multiple insulating films 有权
标题翻译：包括多个绝缘膜的半导体器件
公开(公告)号：US08643021B2
公开(公告)日：2014-02-04
申请号：US13371524
申请日：2012-02-13
申请人： Shunpei Yamazaki , Satoshi Murakami , Masahiko Hayakawa , Kiyoshi Kato , Mitsuaki Osame , Takashi Hirosure , Saishi Fujikawa
发明人： Shunpei Yamazaki , Satoshi Murakami , Masahiko Hayakawa , Kiyoshi Kato , Mitsuaki Osame , Takashi Hirosure , Saishi Fujikawa
IPC分类号： H01L29/04 , H01L29/15 , H01L31/036 , H01L29/10 , H01L31/0376 , H01L31/20 , H01L29/76 , H01L31/112 , H01L31/062 , H01L31/113 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/1244 , G02F1/136204 , H01L21/76804 , H01L21/76831 , H01L27/1248 , H01L27/1255 , H01L27/3244 , H01L29/4908 , H01L29/66757 , H01L29/66765 , H01L29/78621 , H01L29/78645 , H01L51/0037 , Y10S257/906 , Y10S257/908
摘要： A semiconductor display device is formed including an interlayer insulating. Specifically, a TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT.
摘要翻译：形成包括层间绝缘的半导体显示装置。具体地说，形成TFT，然后形成与有机树脂膜相比传递较少水分的含氮无机绝缘膜，以覆盖TFT。接下来，施加包含感光性丙烯酸树脂的有机树脂，并通过将有机树脂膜部分地曝光而形成开口。然后，形成有开口部的有机树脂膜被覆盖有比有机树脂膜透过少的水分的含氮无机绝缘膜。此后，在有机树脂膜的开口部分将栅极绝缘膜和含氮无机绝缘膜的两层部分地蚀刻掉，以暴露TFT的有源层。

4. 发明申请

US20130140577A1 Semiconductor Device and Method for Preparing the Same 审中-公开
标题翻译：半导体器件及其制备方法
公开(公告)号：US20130140577A1
公开(公告)日：2013-06-06
申请号：US13756783
申请日：2013-02-01
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Akira Ishikawa
IPC分类号： H01L29/786
CPC分类号： H01L29/786 , G02F1/136213 , H01L27/124 , H01L27/1248 , H01L27/1255 , H01L29/4908 , H01L29/78648 , Y10S257/903 , Y10S257/906 , Y10S257/908 , Y10S257/924
摘要： A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a drain electrode in a semiconductor device having a thin film transistor and a holding capacitance with three or more capacitance electrodes is provided. Before forming the source electrode and the drain electrode, a crystalline silicon film for relaxing the stress is formed, then a contact hole connecting to the semiconductor film of the thin film transistor is opened, and a metal film to be the source electrode and the drain electrode is formed.
摘要翻译：在具有薄膜晶体管和保持电容的半导体器件中形成源电极和漏电极时由于应力引起的半导体膜，电容电极等的裂纹的半导体器件及其制造方法提供三个或更多个电容电极。在形成源电极和漏电极之前，形成用于缓和应力的晶体硅膜，然后打开与薄膜晶体管的半导体膜连接的接触孔，并将作为源电极和漏极的金属膜形成电极。

5. 发明申请

US20120168903A1 Semiconductor Constructions Containing Tubular Capacitor Storage Nodes, And Retaining Structures Along Portions Of The Tubular Capacitor Storage Nodes 有权
标题翻译：包含管状电容器存储节点和保留结构的半导体结构沿管状电容器存储节点的一部分
公开(公告)号：US20120168903A1
公开(公告)日：2012-07-05
申请号：US13413552
申请日：2012-03-06
申请人： H. Montgomery Manning , Thomas M. Graettinger
发明人： H. Montgomery Manning , Thomas M. Graettinger
IPC分类号： H01L29/02
CPC分类号： H01L27/10894 , H01L27/10817 , H01L27/10852 , H01L28/91 , H01L29/945 , Y10S257/906
摘要： The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.
摘要翻译：本发明包括半导体结构，并且还包括形成多个电容器器件的方法。本发明的示例性方法包括在绝缘材料的开口内形成导电储存节点材料以形成导电容器。形成与至少一些容器物理接触的保持结构格子，随后去除绝缘材料以露出容器的外表面。保持结构可以减轻容器结构的结构完整性的倒塌或其它损失。导电容器对应于第一电容器电极。在容器的外侧壁暴露之后，电介质材料形成在容器内并沿外露的外侧壁。随后，在电介质材料上形成第二电容器电极。第一和第二电容器电极与电介质材料一起形成多个电容器器件。

6. 发明授权

US08154064B2 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US08154064B2
公开(公告)日：2012-04-10
申请号：US12853948
申请日：2010-08-10
申请人： H. Montgomery Manning , Thomas M. Graettinger
发明人： H. Montgomery Manning , Thomas M. Graettinger
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10894 , H01L27/10817 , H01L27/10852 , H01L28/91 , H01L29/945 , Y10S257/906
摘要： The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.
摘要翻译：本发明包括半导体结构，并且还包括形成多个电容器器件的方法。本发明的示例性方法包括在绝缘材料的开口内形成导电储存节点材料以形成导电容器。形成与至少一些容器物理接触的保持结构格子，随后去除绝缘材料以露出容器的外表面。保持结构可以减轻容器结构的结构完整性的倒塌或其它损失。导电容器对应于第一电容器电极。在容器的外侧壁暴露之后，电介质材料形成在容器内并沿外露的外侧壁。随后，在电介质材料上形成第二电容器电极。第一和第二电容器电极与电介质材料一起形成多个电容器器件。

7. 发明申请

US20090020808A1 Semiconductor integrated circuit devices and fabrication methods thereof 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20090020808A1
公开(公告)日：2009-01-22
申请号：US12154046
申请日：2008-05-20
申请人： Man-Jong Yu
发明人： Man-Jong Yu
IPC分类号： H01L29/78 , H01L27/088
CPC分类号： H01L27/10888 , H01L21/28525 , H01L27/10876 , H01L27/10894 , Y10S257/905 , Y10S257/906 , Y10S257/907 , Y10S257/908
摘要： A memory cell of memory device, comprises an active region of a memory cell defined in a semiconductor substrate, and a conductive gate electrode in a trench of the active region. The gate electrode is isolated from the semiconductor substrate. An insulation layer is on the active region and on the conductive gate electrode. A conductive contact is in the insulation layer on the active region at a side of the gate electrode and isolated from the gate electrode. The contact has a first width at a top portion thereof and a second width at a bottom portion thereof, the first width being greater than the second width. The contact is formed of a single-crystal material.
摘要翻译：存储器件的存储单元包括限定在半导体衬底中的存储器单元的有源区和在有源区的沟槽中的导电栅电极。栅电极与半导体衬底隔离。绝缘层位于有源区和导电栅电极上。导电接触位于栅电极一侧的有源区上的绝缘层中，并与栅电极隔离。接触件在其顶部具有第一宽度，在其底部具有第二宽度，第一宽度大于第二宽度。接触由单晶材料形成。

8. 发明授权

US07435670B2 Bit line barrier metal layer for semiconductor device and process for preparing the same 失效
标题翻译：用于半导体器件的位线屏障金属层及其制备方法
公开(公告)号：US07435670B2
公开(公告)日：2008-10-14
申请号：US11842611
申请日：2007-08-21
申请人： Byung Soo Eun
发明人： Byung Soo Eun
IPC分类号： H01L21/28
CPC分类号： H01L23/485 , H01L21/28556 , H01L21/76846 , H01L27/10885 , H01L2924/0002 , Y10S257/906 , Y10S257/907 , H01L2924/00
摘要： The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose an ion implantation region; vapor-depositing a first barrier metal layer of a Ti film on the entire upper surface thereof; and vapor-depositing, on the upper part of the Ti film, a second barrier metal layer of a ZrB2 film having different upper and lower Boron concentrations, by RPECVD controlling the presence/absence of H2 plasma, wherein the barrier metal layer includes the Ti film, lower ZrB2 film and upper a ZrB2 film sequentially stacked between tungsten bit lines and ion implantation region of a semiconductor substrate. Therefore, the present invention can decrease contact resistance between tungsten bit lines and an ion implantation region by utilizing a ZrB2 film having near-amorphous film quality as a barrier metal of tungsten bit lines and thereby preventing diffusion of the dopant doped onto the ion implantation region of a substrate to the outside in a subsequent thermal treatment process, and at the same time, can reduce occurrence of parasitic capacitance between adjacent bit lines by decreasing a thickness of barrier metal layer, thus leading to improved characteristics of the semiconductor device.
摘要翻译：本发明涉及一种用于半导体器件的位线屏障金属层及其制备方法，该方法包括：在气相沉积在衬底上部的绝缘层上形成位线接触，以暴露出离子注入区; 在其整个上表面上蒸镀Ti膜的第一阻挡金属层; 并在Ti膜的上部气相沉积具有不同上和下硼浓度的ZrB 2膜的第二阻挡金属层，通过RPECVD控制H / SUB的存在/不存在 > 2 等离子体，其中阻挡金属层包括依次层叠在钨丝线和离子之间的Ti膜，较低的ZrB 2膜和上部ZrB 2 N 2膜注入区域。因此，本发明可以通过利用具有接近非晶膜质量的ZrB 2 O 2膜作为钨位线的阻挡金属来降低钨位线与离子注入区之间的接触电阻，从而防止在随后的热处理过程中掺杂到衬底的离子注入区域上的掺杂剂到外部的掺杂剂，同时通过减小阻挡金属层的厚度可以减少相邻位线之间的寄生电容的发生，从而导致改善半导体器件的特性。

9. 发明授权

US07435641B2 Low leakage MIM capacitor 有权
公开(公告)号：US07435641B2
公开(公告)日：2008-10-14
申请号：US11932677
申请日：2007-10-31
申请人： Sam Yang
发明人： Sam Yang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10805 , G11C11/404 , G11C2211/4016 , H01L21/76895 , H01L27/10852 , H01L28/56 , H01L28/91 , Y10S257/906 , Y10S438/957
摘要： Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxide buffer layer acts to improve capacitance and reduce capacitor leakage. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

10. 发明申请

US20080239629A1 METHOD AND STRUCTURE FOR REDUCING CRACKS IN A DIELECTRIC LAYER IN CONTACT WITH METAL 有权
标题翻译：用于减少与金属接触的电介质层中的裂纹的方法和结构
公开(公告)号：US20080239629A1
公开(公告)日：2008-10-02
申请号：US11693365
申请日：2007-03-29
申请人： Barry J. Liles , Colin S. Whelan
发明人： Barry J. Liles , Colin S. Whelan
IPC分类号： H01L29/00 , H01G9/00 , H01L21/44
CPC分类号： H01L28/65 , H01L23/5223 , H01L28/75 , H01L2924/0002 , Y10S257/906 , H01L2924/00
摘要： A method and structure for reducing cracks in a dielectric in contact with a metal structure. The metal structure comprises a first metal layer; a second metal layer disposed on, and in contact with the first metal layer, the second metal layer being stiffer than the first metal layer; a third metal layer disposed on, and in contact with the second metal layer, the second metal layer being stiffer than the third metal layer. An additional metal is included wherein the dielectric layer is disposed between the metal structure and the additional metal.
摘要翻译：一种用于减少与金属结构接触的电介质中的裂纹的方法和结构。金属结构包括第一金属层; 设置在第一金属层上并与第一金属层接触的第二金属层，第二金属层比第一金属层更硬; 设置在第二金属层上并与第二金属层接触的第三金属层的第二金属层比第三金属层更硬。包括另外的金属，其中介电层设置在金属结构和附加金属之间。

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