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1. 发明授权

US08154911B2 Memory device and method of writing data to a memory device 有权
标题翻译：存储器件和将数据写入存储器件的方法
公开(公告)号：US08154911B2
公开(公告)日：2012-04-10
申请号：US12762607
申请日：2010-04-19
申请人： Naveen Batra , Rajiv Kumar , Saurabh Agrawal
发明人： Naveen Batra , Rajiv Kumar , Saurabh Agrawal
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C7/12 , G11C8/08 , G11C11/413
摘要： A memory device includes bitlines, wordlines and a matrix of memory cells arranged in rows and columns. Each of the bitlines is electrically connected to memory cells in one of the columns. Each of the wordlines is electrically connected to memory cells in one of the rows. A bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.
摘要翻译：存储器件包括位线，字线和以行和列排列的存储器单元的矩阵。每个位线电连接到一列中的存储单元。每个字线电连接到其中一行中的存储单元。位线写入电压被施加到第一位线。将字线电压施加到第一字线，以将数据写入连接到第一字线和第一位线的第一存储器单元。第一位线和第二位线被电连接用于第一位线和第二位线之间的电荷共享。在电连接第一位线和第二位线之后的预定时间，第一和第二位线被电断开，并且位线写入电压被施加到第二位线。字线电压被施加到第二字线，用于将数据写入连接到第二字线和第二位线的第二存储器单元。

2. 发明申请

US20110149662A1 MEMORY DEVICE AND METHOD OF WRITING DATA TO A MEMORY DEVICE 有权
标题翻译：存储器件和将数据写入存储器件的方法
公开(公告)号：US20110149662A1
公开(公告)日：2011-06-23
申请号：US12762607
申请日：2010-04-19
申请人： Naveen BATRA , Rajiv Kumar , Saurabh Agrawal
发明人： Naveen BATRA , Rajiv Kumar , Saurabh Agrawal
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C8/08 , G11C11/413
摘要： A memory device includes bitlines, wordlines and a matrix of memory cells arranged in rows and columns. Each of the bitlines is electrically connected to memory cells in one of the columns. Each of the wordlines is electrically connected to memory cells in one of the rows. A bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.
摘要翻译：存储器件包括位线，字线和以行和列排列的存储器单元的矩阵。每个位线电连接到一列中的存储单元。每个字线电连接到其中一行中的存储单元。位线写入电压被施加到第一位线。将字线电压施加到第一字线，以将数据写入连接到第一字线和第一位线的第一存储器单元。第一位线和第二位线被电连接用于第一位线和第二位线之间的电荷共享。在电连接第一位线和第二位线之后的预定时间，第一和第二位线被电断开，并且位线写入电压被施加到第二位线。字线电压被施加到第二字线，用于将数据写入连接到第二字线和第二位线的第二存储器单元。

3. 发明授权

US08780615B2 Memory device and method of writing data to a memory device 有权
标题翻译：存储器件和将数据写入存储器件的方法
公开(公告)号：US08780615B2
公开(公告)日：2014-07-15
申请号：US13422906
申请日：2012-03-16
申请人： Naveen Batra , Rajiv Kumar , Saurabh Agrawal
发明人： Naveen Batra , Rajiv Kumar , Saurabh Agrawal
IPC分类号： G11C11/00
CPC分类号： G11C7/12 , G11C8/08 , G11C11/413
摘要： In a memory device, a bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.
摘要翻译：在存储器件中，位线写入电压被施加到第一位线。将字线电压施加到第一字线，以将数据写入连接到第一字线和第一位线的第一存储器单元。第一位线和第二位线被电连接用于第一位线和第二位线之间的电荷共享。在电连接第一位线和第二位线之后的预定时间，第一和第二位线被电断开，并且位线写入电压被施加到第二位线。字线电压被施加到第二字线，用于将数据写入连接到第二字线和第二位线的第二存储器单元。

4. 发明授权

US08259486B2 Self-timed write boost for SRAM cell with self mode control 有权
标题翻译：具有自我模式控制的SRAM单元的自定时写入升压
公开(公告)号：US08259486B2
公开(公告)日：2012-09-04
申请号：US12571170
申请日：2009-09-30
申请人： Ashish Kumar , Naveen Batra
发明人： Ashish Kumar , Naveen Batra
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C5/145
摘要： A write boost circuit provides an automatic mode control for boost with different modalities with respect to the external supply voltage and also with respect to the extent of boost required at different process corners. The write boost circuit also takes care of the minimum boost provided to process corners with good writability where less boost is required. The boost is realized in terms of ground raising in the particular context and in general applicable to all other methods.
摘要翻译：写升压电路提供了一种自动模式控制，用于相对于外部电源电压的不同模式的升压，以及相对于不同工艺角所需的升压程度。写升压电路还负责处理拐角的最小提升，具有良好的写入性，需要较少的增压。在特定情况下，通过地面提升实现提升，一般适用于所有其他方法。

5. 发明申请

US20100115385A1 DETECTING DATA-ACCESS-ELEMENT-SELECTION ERRORS DURING DATA ACCESS IN DATA-STORAGE ARRAYS 审中-公开
标题翻译：在数据存储阵列中检测数据访问期间的数据访问元素选择错误
公开(公告)号：US20100115385A1
公开(公告)日：2010-05-06
申请号：US12613399
申请日：2009-11-05
申请人： NAVEEN BATRA , JITENDRA DASANI
发明人： NAVEEN BATRA , JITENDRA DASANI
IPC分类号： G06F11/07
CPC分类号： G06F11/0751 , G06F11/0727 , G06F11/0772 , G11C29/02 , G11C29/024 , G11C2029/0409
摘要： An embodiment of the present disclosure relates to detection of data access element selection errors during data access in data storage arrays. An embodiment of the disclosure describes a system including a data storage array comprising a first and a second error identifier. The error identifiers generate an error signal in case multiple data access elements are selected or no data access element is selected, respectively. A system for detection of data-access-element-selection errors further comprises a common error-signal generator which provides an output when an error signal is generated by either of said error identifiers.
摘要翻译：本公开的实施例涉及在数据存储阵列中的数据访问期间检测数据访问元素选择错误。本公开的实施例描述了包括包括第一和第二错误标识符的数据存储阵列的系统。在选择多个数据访问元素或没有选择数据访问元素的情况下，错误标识符生成错误信号。用于检测数据访问元件选择错误的系统还包括公共误差信号发生器，当由所述错误标识符中的任一个生成错误信号时，该误差信号发生器提供输出。

6. 发明申请

US20120224440A1 MEMORY DEVICE AND METHOD OF WRITING DATA TO A MEMORY DEVICE 有权
标题翻译：存储器件和将数据写入存储器件的方法
公开(公告)号：US20120224440A1
公开(公告)日：2012-09-06
申请号：US13422906
申请日：2012-03-16
申请人： Naveen BATRA , Rajiv Kumar , Saurabh Agrawal
发明人： Naveen BATRA , Rajiv Kumar , Saurabh Agrawal
IPC分类号： G11C7/12 , G11C7/10 , G11C7/00
CPC分类号： G11C7/12 , G11C8/08 , G11C11/413
摘要： In a memory device, a bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.
摘要翻译：在存储器件中，位线写入电压被施加到第一位线。将字线电压施加到第一字线，以将数据写入连接到第一字线和第一位线的第一存储器单元。第一位线和第二位线被电连接用于第一位线和第二位线之间的电荷共享。在电连接第一位线和第二位线之后的预定时间，第一和第二位线被电断开，并且位线写入电压被施加到第二位线。字线电压被施加到第二字线，用于将数据写入连接到第二字线和第二位线的第二存储器单元。

7. 发明申请

US20110026309A1 SELF-TIMED WRITE BOOST FOR SRAM CELL WITH SELF MODE CONTROL 有权
标题翻译：用于具有自我模式控制的SRAM单元的自定时写入
公开(公告)号：US20110026309A1
公开(公告)日：2011-02-03
申请号：US12571170
申请日：2009-09-30
申请人： Ashish KUMAR , Naveen Batra
发明人： Ashish KUMAR , Naveen Batra
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C11/413 , G11C5/145
摘要： A write boost circuit provides an automatic mode control for boost with different modalities with respect to the external supply voltage and also with respect to the extent of boost required at different process corners. The write boost circuit also takes care of the minimum boost provided to process corners with good writability where less boost is required. The boost is realized in terms of ground raising in the particular context and in general applicable to all other methods.
摘要翻译：写升压电路提供了一种自动模式控制，用于相对于外部电源电压的不同模式的升压，以及相对于不同工艺角所需的升压程度。写升压电路还负责处理拐角的最小提升，具有良好的写入性，需要较少的提升。在特定情况下，通过地面提升实现提升，一般适用于所有其他方法。

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