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1. 发明申请

US20140247673A1 ROW SHIFTING SHIFTABLE MEMORY 审中-公开
标题翻译：滚动移位存储器
公开(公告)号：US20140247673A1
公开(公告)日：2014-09-04
申请号：US14349401
申请日：2011-10-28
申请人： Naveen Muralimanohar , Hans Boehm
发明人： Naveen Muralimanohar , Hans Boehm
IPC分类号： G11C11/4094 , G11C11/419
CPC分类号： G11C11/4094 , G11C7/1006 , G11C11/408 , G11C11/418 , G11C11/419 , G11C19/188 , G11C19/287
摘要： A shiftable memory employs row shifting to shift data along a row. The shiftable memory includes memory cells arranged as a plurality of rows and a plurality of columns. The shiftable memory further includes shift logic to shift data from an output of a first column to an input of a second column. The shifted data is provided by a memory cell of the first column in a selected row. The shifted data is received and stored by a memory cell in the selected row of the second column. The shift logic facilitates shifting data along the selected row.
摘要翻译：可移位存储器使用行移位来沿着一行移位数据。可移位存储器包括布置成多行和多列的存储单元。可移位存储器还包括移位逻辑以将数据从第一列的输出移位到第二列的输入。移位的数据由选定行中的第一列的存储单元提供。移位的数据由第二列的所选行中的存储单元接收和存储。移位逻辑有助于沿所选择的行移动数据。

2. 发明授权

US08788904B2 Methods and apparatus to perform error detection and correction 有权
标题翻译：执行错误检测和校正的方法和装置
公开(公告)号：US08788904B2
公开(公告)日：2014-07-22
申请号：US13285742
申请日：2011-10-31
申请人： Sheng Li , Norman Paul Jouppi , Naveen Muralimanohar
发明人： Sheng Li , Norman Paul Jouppi , Naveen Muralimanohar
IPC分类号： H03M13/00
CPC分类号： G06F11/1064
摘要： Example methods, apparatus, and articles of manufacture to perform error detection and correction are disclosed. A disclosed example method involves enabling a memory controller to operate in one of a tagged memory mode or a non-tagged memory mode. In addition, when the tagged memory mode is enabled in the memory controller, a five-error-correction-six-error-detection per-burst mode is selected to perform error correction on data. When the non-tagged memory mode is enabled in the memory controller, one of a six-error-correction-seven-error-detection per-burst mode or a single-error-correction-dual-error-detection per-transfer mode is selected based on a pattern of error types in the data.
摘要翻译：公开了用于执行错误检测和校正的示例性方法，装置和制造。所公开的示例性方法涉及使存储器控制器能够以标记存储器模式或非标记存储器模式之一进行操作。另外，当在存储器控制器中启用标记存储器模式时，选择五错误校正六错误检测每脉冲串模式以对数据执行纠错。当在存储器控制器中启用非标记存储器模式时，每个突发模式的六错误校正七错误检测或单错误校正双错误检测每传输模式之一是根据数据中的错误类型的模式进行选择。

3. 发明申请

US20120278651A1 Remapping data with pointer 有权
标题翻译：用指针重新映射数据
公开(公告)号：US20120278651A1
公开(公告)日：2012-11-01
申请号：US13066976
申请日：2011-04-28
申请人： Naveen Muralimanohar , Doe Hyun Yoon , Jichuan Chang , Parthasarathy Ranganathan , Norman Paul Jouppi
发明人： Naveen Muralimanohar , Doe Hyun Yoon , Jichuan Chang , Parthasarathy Ranganathan , Norman Paul Jouppi
IPC分类号： G06F11/20
CPC分类号： G06F11/20 , G11C29/76
摘要： Embodiments herein relate to a method for remapping data. In an embodiment, it is determined if a first memory block is faulty. A pointer is stored to the first memory block and a pointer flag of the first memory block is set when the first memory block is faulty. Data previously stored at the first memory block is written to a second memory block, where the pointer points to a location of the second memory block.
摘要翻译：本文的实施例涉及用于重新映射数据的方法。在一个实施例中，确定第一存储器块是否有故障。指针被存储到第一存储器块，并且当第一存储器块发生故障时，设置第一存储器块的指针标志。先前存储在第一存储器块的数据被写入第二存储器块，其中指针指向第二存储器块的位置。

4. 发明申请

US20120268983A1 RANDOM-ACCESS MEMORY WITH DYNAMICALLY ADJUSTABLE ENDURANCE AND RETENTION 有权
标题翻译：具有动态可调节的持久性和持续性的随机存取记忆
公开(公告)号：US20120268983A1
公开(公告)日：2012-10-25
申请号：US13092789
申请日：2011-04-22
申请人： Naveen Muralimanohar , Jichuan Chang , Parthasarathy Ranganathan
发明人： Naveen Muralimanohar , Jichuan Chang , Parthasarathy Ranganathan
IPC分类号： G11C11/00
CPC分类号： G11C29/028 , G11C13/0004 , G11C13/0035 , G11C13/0061 , G11C13/0069 , G11C29/021 , G11C29/50016 , G11C2013/0078
摘要： A memory device is provided. The memory device comprises an array of memory cells, each including a volume of material that can stably exhibit at least two different physical states that are each associated with a different data value, word lines that each interconnects a row of memory cells within the array of memory cells to a word-line driver, and bit lines that each interconnects a column of memory cells, through a bit-line driver, to a write driver that is controlled, during a WRITE operation, to write an input data value to an activated memory cell at the intersection of the column of memory cells and an activated row of memory cells by generating a current density within the memory cells that corresponds to retention/endurance characteristics of the memory cell dynamically assigned to the memory cell by a memory controller, operating system, or other control functionality.
摘要翻译：提供存储器件。存储器件包括存储器单元阵列，每个存储器单元包括能够稳定地呈现与不同数据值相关联的至少两种不同物理状态的材料体积，每条相互连接在该阵列内的一行存储器单元的字线存储器单元到字线驱动器，以及位线，其每一个通过位线驱动器将存储器单元的列互连到在写操作期间被控制的写驱动器，以将输入数据值写入激活的通过在存储器单元内产生对应于由存储器控制器动态地分配给存储器单元的存储器单元的保持/耐久特性的电流密度，在存储器单元列和激活的存储器单元行的交点处存储单元，操作系统或其他控制功能。

5. 发明申请

US20110246828A1 Memory Checkpointing Using A Co-Located Processor and Service Processor 有权
标题翻译：使用位于处理器和服务处理器的内存检查点
公开(公告)号：US20110246828A1
公开(公告)日：2011-10-06
申请号：US12751005
申请日：2010-03-31
申请人： Matteo Monchiero , Naveen Muralimanohar , Partha Ranganathan
发明人： Matteo Monchiero , Naveen Muralimanohar , Partha Ranganathan
IPC分类号： G06F11/07 , G06F12/00 , G06F13/14
CPC分类号： G06F11/1402 , G06F11/1438 , G06F11/1658 , G06F11/2025 , G06F11/2035 , G06F11/2097
摘要： A system and method is shown that includes a processor operatively connected to a memory, the processor to include a memory controller to control access to the memory. The system and method also includes a service processor, co-located on a common board and operatively connected to the processor and the memory, the service processor to include an additional memory controller to control access to the memory as part of a checkpoint regime.
摘要翻译：示出了包括可操作地连接到存储器的处理器的系统和方法，所述处理器包括存储器控制器以控制对存储器的访问。该系统和方法还包括服务处理器，共同位于公共板上并且可操作地连接到处理器和存储器，服务处理器包括附加存储器控制器以控制对作为检查点状态的一部分的对存储器的访问。

6. 发明授权

US09411757B2 Memory interface 有权
标题翻译：内存界面
公开(公告)号：US09411757B2
公开(公告)日：2016-08-09
申请号：US14005196
申请日：2011-03-14
申请人： Aniruddha Nagendran Udipi , Naveen Muralimanohar , Norman Paul Jouppi , Rajeev Balasubramonian , Alan Lynn Davis
发明人： Aniruddha Nagendran Udipi , Naveen Muralimanohar , Norman Paul Jouppi , Rajeev Balasubramonian , Alan Lynn Davis
IPC分类号： G06F13/16 , G06F13/362 , G06F13/38
CPC分类号： G06F13/3625 , G06F13/1605 , G06F13/1689
摘要： The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing as read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation.
摘要翻译：本公开提供了一种用于处理存储器存取操作的方法。该方法包括至少部分地基于存储器模块的总存储器延迟来确定固定响应时间。该方法还包括通过数据总线识别从存储器模块接收返回数据的可用时隙，其中当前时钟周期与可用时隙之间的时间差大于或等于固定响应时间。该方法还包括通过预留可用时隙来创建第一时隙预留。该方法还包括通过数据总线向存储器模块发出读取请求，其中读取请求以从第一时隙预留时间减去固定响应时间确定的时钟周期发出。

7. 发明授权

US09298621B2 Managing chip multi-processors through virtual domains 有权
标题翻译：通过虚拟域管理芯片多处理器
公开(公告)号：US09298621B2
公开(公告)日：2016-03-29
申请号：US13288996
申请日：2011-11-04
申请人： Sheng Li , Norman Paul Jouppi , Naveen Muralimanohar
发明人： Sheng Li , Norman Paul Jouppi , Naveen Muralimanohar
IPC分类号： G06F12/10 , G06F12/08 , G06F15/173 , G06F9/50 , G06F12/02 , G06F12/00
CPC分类号： G06F12/0813 , G06F9/5077 , G06F12/0817 , G06F12/10 , G06F12/1045 , G06F15/17381 , G06F2212/2542 , Y02D10/13 , Y02D10/22 , Y02D10/36
摘要： A chip multi-processor (CMP) with virtual domain management. The CMP has a plurality of tiles each including a core and a cache, a mapping storage, a plurality of memory controllers, a communication bus interconnecting the tiles and the memory controllers, and machine-executable instructions. The tiles and memory controllers are responsive to the instructions to group the tiles into a plurality of virtual domains, each virtual domain associated with at least one memory controller, and to store a mapping unique to each virtual domain in the mapping storage.
摘要翻译：具有虚拟域管理的芯片多处理器（CMP）。 CMP具有多个瓦片，每个瓦片包括核心和高速缓存，映射存储器，多个存储器控制器，互连瓦片和存储器控制器的通信总线以及机器可执行指令。瓦片和存储器控制器响应于将瓦片分组成多个虚拟域，与至少一个存储器控制器相关联的每个虚拟域以及存储映射存储器中的每个虚拟域唯一的映射的指令。

8. 发明申请

US20140208156A1 MEMORY ACCESS METHODS AND APPARATUS 有权
标题翻译：存储器访问方法和设备
公开(公告)号：US20140208156A1
公开(公告)日：2014-07-24
申请号：US13387714
申请日：2011-01-27
申请人： Naveen Muralimanohar , Aniruddha Udipi , Chatterjee Niladrish , Balasubramonian Rajeev , Alan Lynn Davis , Norman Paul Jouppi
发明人： Naveen Muralimanohar , Aniruddha Udipi , Chatterjee Niladrish , Balasubramonian Rajeev , Alan Lynn Davis , Norman Paul Jouppi
IPC分类号： G11C7/10 , G06F11/10
CPC分类号： G06F3/0625 , G06F3/0634 , G06F3/0658 , G06F3/0673 , G06F11/1088 , G06F12/0802 , G06F12/0893 , G06F2212/1028 , G06F2212/3042 , G06F2212/305 , G11C5/04 , G11C7/10 , G11C8/12 , G11C11/4082 , Y02D10/13
摘要： A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder (606) to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.
摘要翻译：所公开的示例性装置包括用于将对应于行（608）的行地址存储在存储器阵列（602）中的行地址寄存器（412）。示例性装置还包括耦合到行地址寄存器的行解码器（604），用于在存储器接收列地址之后，在行的字线（704）上断言信号。另外，示例性装置包括列解码器（606），用于基于列地址和在字线上断言的信号选择性地激活该行的一部分。

9. 发明申请

US20140040518A1 MEMORY INTERFACE 有权
标题翻译：记忆界面
公开(公告)号：US20140040518A1
公开(公告)日：2014-02-06
申请号：US14005196
申请日：2011-03-14
申请人： Aniruddha Nagendran Udipi , Naveen Muralimanohar , Norman Paul Jouppi , Rajeev Balasubramonian , Alan Lynn Davis
发明人： Aniruddha Nagendran Udipi , Naveen Muralimanohar , Norman Paul Jouppi , Rajeev Balasubramonian , Alan Lynn Davis
IPC分类号： G06F13/362
CPC分类号： G06F13/3625 , G06F13/1605 , G06F13/1689
摘要： The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing as read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation.
摘要翻译：本公开提供了一种用于处理存储器存取操作的方法。该方法包括至少部分地基于存储器模块的总存储器延迟来确定固定响应时间。该方法还包括通过数据总线识别从存储器模块接收返回数据的可用时隙，其中当前时钟周期与可用时隙之间的时间差大于或等于固定响应时间。该方法还包括通过预留可用时隙来创建第一时隙预留。该方法还包括通过数据总线向存储器模块发出读取请求，其中读取请求以从第一时隙预留时间减去固定响应时间确定的时钟周期发出。

10. 发明授权

US08516271B2 Securing non-volatile memory regions 有权
标题翻译：保护非易失性存储器区域
公开(公告)号：US08516271B2
公开(公告)日：2013-08-20
申请号：US13046381
申请日：2011-03-11
申请人： Paolo Faraboschi , Parthasarathy Ranganathan , Naveen Muralimanohar
发明人： Paolo Faraboschi , Parthasarathy Ranganathan , Naveen Muralimanohar
IPC分类号： H04L9/14 , H04L9/30
CPC分类号： G06F12/0246 , G06F12/1441 , G06F12/1466 , G06F2212/225
摘要： Methods, apparatus and articles of manufacture to secure non-volatile memory regions are disclosed. An example method disclosed herein comprises associating a first key pair and a second key pair different than the first key pair with a process, using the first key pair to secure a first region of a non-volatile memory for the process, and using the second key pair to secure a second region of the non-volatile memory for the same process, the second region being different than the first region.
摘要翻译：公开了用于安全非易失性存储器区域的方法，装置和制品。本文公开的示例性方法包括：使用第一密钥对来将与第一密钥对不同的第一密钥对和第二密钥对与过程相关联，以使得用于该过程的非易失性存储器的第一区域被固定，并且使用第二密钥对密钥对以固定用于相同处理的非易失性存储器的第二区域，第二区域不同于第一区域。

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