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1. 发明申请

US20160034528A1 CO-PROCESSOR-BASED ARRAY-ORIENTED DATABASE PROCESSING 审中-公开
标题翻译：基于CO处理器的面向阵列的数据库处理
公开(公告)号：US20160034528A1
公开(公告)日：2016-02-04
申请号：US14775329
申请日：2013-03-15
申请人： Indrajit ROY , Feng LIU , Vanish TALWAR , Shimin CHEN , Jichuan CHANG , Parthasarathy RANGANATHAN , HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： Indrajit Roy , Feng Liu , Vanish Talwar , Shimin Chen , Jichuan Chang , Parthasarathy Ranganathan
IPC分类号： G06F17/30
CPC分类号： G06F16/245 , G06F9/5005 , G06F9/5066 , G06F16/21 , G06F16/24554 , G06F16/283
摘要： A technique includes receiving a user input in an array-oriented database. The user input indicates a database operation and processing a plurality of chunks of data stored by the database to perform the operation. The processing in dudes selectively distributing the processing of the plurality of chunks between a first group of at least one central processing unit and a second group of at least one co-processor.
摘要翻译：一种技术包括在面向数组的数据库中接收用户输入。用户输入指示数据库操作并处理由数据库存储的多个数据块以执行操作。所述处理在所述至少一个中央处理单元的第一组和至少一个协处理器的第二组之间选择性地分布所述多个块的处理。

2. 发明申请

US20150193158A1 SMART MEMORY BUFFERS 有权
公开(公告)号：US20150193158A1
公开(公告)日：2015-07-09
申请号：US14417220
申请日：2012-10-30
申请人： Doe Hyun Yoon , Naveen Murali-Manohar , Jichuan Chang , Parthasarathy Ranganathan
发明人： Doe Hyun Yoon , Naveen Murali-Manohar , Jichuan Chang , Parthasarathy Ranganathan
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/065 , G06F3/0655 , G06F3/0656 , G06F3/0665 , G06F3/0688 , G06F3/0689 , G06F11/108 , G06F2211/1054 , G06F2211/1066
摘要： An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.
摘要翻译：一种示例性方法涉及在第一存储器节点处接收要写入第一存储器节点中的存储器位置的数据。从设备接收数据。在第一个存储器节点，从存储器位置读取旧数据，而不将旧数据发送到设备。数据被写入存储器位置。将数据和旧数据从第一存储器节点发送到第二存储器节点，以将奇偶校验信息存储在第二存储器节点中，而不需要设备确定奇偶校验信息。奇偶校验信息基于存储在第一存储器节点中的数据。

3. 发明授权

US08683125B2 Tier identification (TID) for tiered memory characteristics 有权
标题翻译：分层记忆特征的层次识别（TID）
公开(公告)号：US08683125B2
公开(公告)日：2014-03-25
申请号：US13286681
申请日：2011-11-01
申请人： Jichuan Chang , Kevin T Lim , Parthasarathy Ranganathan
发明人： Jichuan Chang , Kevin T Lim , Parthasarathy Ranganathan
IPC分类号： G06F12/00
CPC分类号： G06F12/10 , G06F9/5016 , G06F2212/205
摘要： A tier identification (TID) is to indicate a characteristic of a memory region associated with a virtual address in a tiered memory system. A thread may be serviced according to a first path based on the TID indicating a first characteristic. The thread may be serviced according to a second path based on the TID indicating a second characteristic.
摘要翻译：层标识（TID）是指示与分层存储器系统中的虚拟地址相关联的存储器区域的特性。可以基于指示第一特征的TID根据第一路径来服务线程。可以基于指示第二特征的TID根据第二路径来服务线程。

4. 发明申请

US20140040528A1 RECONFIGURABLE CROSSBAR NETWORKS 有权
标题翻译：可重构的十字路口网络
公开(公告)号：US20140040528A1
公开(公告)日：2014-02-06
申请号：US13563074
申请日：2012-07-31
申请人： Jichuan Chang , Parthasarathy Ranganathan , Kevin T. Lim
发明人： Jichuan Chang , Parthasarathy Ranganathan , Kevin T. Lim
IPC分类号： G06F13/36
CPC分类号： G06F13/36 , G06F13/14 , G06F13/38 , G06F13/40 , G06F13/4022
摘要： Reconfigurable crossbar networks, and devices, systems and methods, including hardware in the form of logic (e.g. application specific integrated circuits (ASICS)), and software in the form of machine readable instructions stored on machine readable media (e.g., flash, non-volatile memory, etc.), which implement the same, are provided. An example of a reconfigurable crossbar network includes a crossbar. A plurality of endpoints is coupled to the crossbar. The plurality of endpoints is grouped into regions at design time of the crossbar network. A plurality of regional interconnects are provided. Each regional interconnect connects a group of endpoints within a given region.
摘要翻译：可重构的交叉网络以及设备，系统和方法，包括逻辑形式的硬件（例如专用集成电路（ASICS））以及存储在机器可读介质（例如，闪存，易失性存储器等），其实现相同。可重构交叉网络的示例包括交叉开关。多个端点耦合到横杆。多个端点在交叉网络的设计时被分组成区域。提供了多个区域互连。每个区域互连连接给定区域内的一组端点。

5. 发明申请

US20130339468A1 NON-VOLATILE MEMORY PHYSICAL NETWORKS 有权
标题翻译：非易失性存储器物理网络
公开(公告)号：US20130339468A1
公开(公告)日：2013-12-19
申请号：US13524659
申请日：2012-06-15
申请人： Jichuan Chang , Parthasarathy Ranganathan
发明人： Jichuan Chang , Parthasarathy Ranganathan
IPC分类号： G06F15/167 , H04W8/00
CPC分类号： G06F17/30 , G06F11/00
摘要： A method for communication between computing devices includes identifying the parameters of a data transfer between a source computing device and a target computing device and identifying communication paths between a source computing device and target computing device, in which at least one of the communications paths is a physical network. A communication path is selected for the data transfer. When a data transfer over the physical network is selected as a communication path, a nonvolatile memory (NVM) unit is removed from the source computing device and placed in a cartridge and the cartridge is programmed with transfer information. The NVM unit and cartridge are transported through the physical network to the target computing device according to the transfer information and the NVM unit is electrically connected to the target computing device.
摘要翻译：用于计算设备之间的通信的方法包括识别源计算设备和目标计算设备之间的数据传输的参数，以及识别源计算设备与目标计算设备之间的通信路径，其中至少一个通信路径为物理网络。选择通信路径进行数据传输。当通过物理网络的数据传输被选择为通信路径时，从源计算设备移除非易失性存储器（NVM）单元并将其放置在盒中，并且用传送信息对盒进行编程。 NVM单元和盒式磁带根据传输信息通过物理网络传输到目标计算设备，并且NVM单元电连接到目标计算设备。

6. 发明申请

US20130329491A1 Hybrid Memory Module 审中-公开
标题翻译：混合内存模块
公开(公告)号：US20130329491A1
公开(公告)日：2013-12-12
申请号：US13494761
申请日：2012-06-12
申请人： Jichuan Chang , Doe Hyun Yoon , Parthasarathy Ranganathan
发明人： Jichuan Chang , Doe Hyun Yoon , Parthasarathy Ranganathan
IPC分类号： G11C7/10 , G11C11/00 , G11C16/04
CPC分类号： G11C5/04 , G11C11/005
摘要： A hybrid. memory module. The module includes at least two heterogeneous memory devices and a memory buffer in communication with the memory devices to read data from any one of the memory devices and write the data to any other of the memory devices.
摘要翻译：混合动力内存模块该模块包括至少两个异构存储器件和与存储器件通信的存储器缓冲器，以从存储器件中的任何一个读取数据，并将数据写入存储器件中的任何其它存储器件。

7. 发明申请

US20130227218A1 Data Migration between Memory Locations 有权
标题翻译：内存位置之间的数据迁移
公开(公告)号：US20130227218A1
公开(公告)日：2013-08-29
申请号：US13408276
申请日：2012-02-29
申请人： Jichuan Chang , Justin James Meza , Parthasarathy Ranganathan
发明人： Jichuan Chang , Justin James Meza , Parthasarathy Ranganathan
IPC分类号： G06F12/16 , G06F12/08
CPC分类号： G06F12/0866 , G06F2212/214
摘要： Migrating data may include determining to copy a first data block in a first memory location to a second memory location and determining to copy a second data block in the first memory location to the second memory location based on a migration policy.
摘要翻译：迁移数据可以包括确定将第一存储器位置中的第一数据块复制到第二存储器位置，并且基于迁移策略确定将第一存储器位置中的第二数据块复制到第二存储器位置。

8. 发明授权

US08516271B2 Securing non-volatile memory regions 有权
标题翻译：保护非易失性存储器区域
公开(公告)号：US08516271B2
公开(公告)日：2013-08-20
申请号：US13046381
申请日：2011-03-11
申请人： Paolo Faraboschi , Parthasarathy Ranganathan , Naveen Muralimanohar
发明人： Paolo Faraboschi , Parthasarathy Ranganathan , Naveen Muralimanohar
IPC分类号： H04L9/14 , H04L9/30
CPC分类号： G06F12/0246 , G06F12/1441 , G06F12/1466 , G06F2212/225
摘要： Methods, apparatus and articles of manufacture to secure non-volatile memory regions are disclosed. An example method disclosed herein comprises associating a first key pair and a second key pair different than the first key pair with a process, using the first key pair to secure a first region of a non-volatile memory for the process, and using the second key pair to secure a second region of the non-volatile memory for the same process, the second region being different than the first region.
摘要翻译：公开了用于安全非易失性存储器区域的方法，装置和制品。本文公开的示例性方法包括：使用第一密钥对来将与第一密钥对不同的第一密钥对和第二密钥对与过程相关联，以使得用于该过程的非易失性存储器的第一区域被固定，并且使用第二密钥对密钥对以固定用于相同处理的非易失性存储器的第二区域，第二区域不同于第一区域。

9. 发明申请

US20120272039A1 RETENTION-VALUE ASSOCITED MEMORY 有权
标题翻译：保留价值相关记忆
公开(公告)号：US20120272039A1
公开(公告)日：2012-10-25
申请号：US13092911
申请日：2011-04-23
申请人： Naveen Muralimanohar , Jichuan Chang , Parthasarathy Ranganathan
发明人： Naveen Muralimanohar , Jichuan Chang , Parthasarathy Ranganathan
IPC分类号： G06F12/06
CPC分类号： G06F12/0292 , G06F12/0638 , Y02D10/13
摘要： A memory component or subsystem is provided. The memory comprises one or more memory devices and one or more write controllers within each of the one or more memory devices that each controls memory-device components to write input data values into a plurality of memory cells within a memory device that represents a unit of stored data addressed by a logical-address-space address, the write controller applying a current to the plurality of memory cells during a WRITE operation with a magnitude that corresponds to a retention value associated with the logical-address-space address.
摘要翻译：提供存储器组件或子系统。存储器包括一个或多个存储器设备和一个或多个存储器设备内的每一个中的一个或多个写入控制器，每个存储器设备各自控制存储器设备组件以将输入数据值写入到存储器设备内的多个存储器单元中，由逻辑地址空间地址寻址的存储的数据，所述写入控制器在写入操作期间以对应于与所述逻辑地址空间地址相关联的保留值的大小施加电流到所述多个存储器单元。

10. 发明申请

US20120254507A1 WRITE-ABSORBING BUFFER FOR NON-VOLATILE MEMORY 有权
标题翻译：用于非易失性存储器的写吸收缓冲器
公开(公告)号：US20120254507A1
公开(公告)日：2012-10-04
申请号：US13077842
申请日：2011-03-31
申请人： Jichuan Chang , Parthasarathy Ranganathan , David Roberts
发明人： Jichuan Chang , Parthasarathy Ranganathan , David Roberts
IPC分类号： G06F12/02
CPC分类号： G06F12/0868 , G06F11/1441 , G06F11/2015 , G06F12/0804 , G06F2212/2024 , Y02D10/13
摘要： A write-absorbing, volatile memory buffer for use with a processor module and a non-volatile memory is disclosed. The write-absorbing buffer operates as a dirty cache that can be used to look up both read and write requests, although allocating new blocks only for write requests and not read requests. The blocks are small sized, and a write-only least-recently used cache replacement policy is used to transfer data in the blocks to the non-volatile memory. The write-absorbing buffer can be used to store copy-on-write pages for at least one virtual machine associated with the processor module and reduce write overhead to the non-volatile memory.
摘要翻译：公开了一种与处理器模块和非易失性存储器一起使用的写吸收式易失性存储器缓冲器。写缓冲缓冲区作为一个脏高速缓存，可用于查找读写请求，尽管只为写请求而不是读请求分配新块。这些块是小尺寸的，并且只写最少最近使用的高速缓存替换策略用于将块中的数据传送到非易失性存储器。写吸收缓冲器可用于存储与处理器模块相关联的至少一个虚拟机的写时复制页面，并减少对非易失性存储器的写入开销。

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