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    • 1. 发明授权
    • Digital phase locked loop
    • 数字锁相环
    • US08362815B2
    • 2013-01-29
    • US12978221
    • 2010-12-23
    • Nenad PavlovicJozef Reinerus Maria Bergervoet
    • Nenad PavlovicJozef Reinerus Maria Bergervoet
    • H03L7/06
    • H03L7/18H03L7/081H03L7/0991
    • A digital phase locked loop (300) configured to receive a reference clock signal (302) and a channel control word (308), and to generate an output clock signal (304). The digital phase locked loop comprising an adjustable delay component (306) configured to: receive the reference clock signal (302), apply a time delay to the reference clock signal (302) in accordance with a time delay control signal (316); and provide a delayed reference clock signal (318). The digital phase locked loop further comprising a timing component (320) configured to process the delayed reference clock signal (318) and the output clock signal (304), and generate a first control signal (322) representative of the phase of the output clock signal (304); a reference accumulator (310) configured to receive the channel command word (308) and generate: a second control signal (312) representative of the phase of an intended output clock signal; and the time delay control signal (316) such that the delayed reference clock signal (318) is delayed by a period of time representative of a first portion of the phase of the intended output clock signal. The digital phase locked loop also comprising a controller (314) configured to process the first and second control signals (322, 312), and generate a DCO control signal (326) for setting the frequency of a digitally controlled oscillator (328) in accordance with the first and second control signals (322, 312); and a digitally controlled oscillator (328) configured to generate the output clock signal (304) in accordance with the DCO control signal (326).
    • 数字锁相环(300),被配置为接收参考时钟信号(302)和信道控制字(308),并产生输出时钟信号(304)。 数字锁相环包括可调节延迟部件(306),其被配置为:接收参考时钟信号(302),根据时间延迟控制信号(316)对参考时钟信号(302)施加时间延迟; 并提供延迟的参考时钟信号(318)。 数字锁相环还包括被配置为处理延迟的参考时钟信号(318)和输出时钟信号(304)的定时组件(320),并且产生表示输出时钟的相位的第一控制信号(322) 信号(304); 参考累加器(310),被配置为接收所述信道命令字(308)并产生:表示预期输出时钟信号的相位的第二控制信号(312); 和时间延迟控制信号(316),使得延迟的参考时钟信号(318)被延迟表示期望输出时钟信号的相位的第一部分的时间段。 数字锁相环还包括被配置为处理第一和第二控制信号(322,312)的控制器(314),并且产生用于根据数字控制振荡器(328)的频率设置的DCO控制信号(326) 具有第一和第二控制信号(322,312); 和配置成根据DCO控制信号(326)产生输出时钟信号(304)的数控振荡器(328)。
    • 4. 发明授权
    • Generation of device dependent RSA key
    • 生成与设备有关的RSA密钥
    • US08472620B2
    • 2013-06-25
    • US11763564
    • 2007-06-15
    • Nenad Pavlovic
    • Nenad Pavlovic
    • H04L9/08H04L9/12
    • H04L9/302H04L2209/80H04W12/04
    • A portable electronic device for exchanging encrypted data with other electronic devices includes a processor, a memory operatively coupled to the processor, and a prime number generation circuit operatively coupled to the processor and memory. The prime number generation circuit includes logic that generates at least two prime numbers based on unique data stored in the electronic device, wherein said at least two prime numbers are always the same at least two prime numbers. The generated prime numbers then can be used to generate RSA public and private keys within the electronic device.
    • 用于与其他电子设备交换加密数据的便携式电子设备包括处理器,可操作地耦合到处理器的存储器和可操作地耦合到处理器和存储器的素数生成电路。 质数产生电路包括基于存储在电子设备中的唯一数据生成至少两个素数的逻辑,其中所述至少两个素数总是至少两个素数相同。 所产生的素数然后可以用于在电子设备内生成RSA公钥和私钥。
    • 5. 发明申请
    • Digital Modulator
    • 数字调制器
    • US20110261914A1
    • 2011-10-27
    • US13001894
    • 2009-07-01
    • Xin HeJan Van SinderenManuel Collados AsensioNenad Pavlovic
    • Xin HeJan Van SinderenManuel Collados AsensioNenad Pavlovic
    • H04L7/00
    • H03C5/00
    • The present application relates to a digital modulator comprising an output stage comprising a number of unit cell arrays, and a sampling stage. The present application relates also to a communication device comprising said digital modulator, a method for digitally modulating and a computer program product. More particularly, the digital modulator comprises an output stage comprising a number of unit cell arrays, wherein the output stage comprises at least one carrier frequency signal input terminal configured to receive a carrier frequency signal. The digital modulator comprises a sampling stage connectable to the output stage, wherein the sampling stage is configured to oversample at least one data input signal. The digital modulator comprises at least one sampling clock generating device configured to generate at least one sampling clock signal depending on the number of arranged unit cell arrays and the carrier frequency signal.
    • 本申请涉及一种数字调制器,其包括包括多个单元阵列的输出级和采样级。 本申请还涉及包括所述数字调制器,数字调制方法和计算机程序产品的通信设备。 更具体地,数字调制器包括包括多个单元阵列的输出级,其中输出级包括被配置为接收载波频率信号的至少一个载波频率信号输入端。 数字调制器包括可连接到输出级的采样级,其中采样级被配置为对至少一个数据输入信号进行过采样。 数字调制器包括至少一个采样时钟产生装置,其被配置为根据排列的单元阵列的数量和载波频率信号产生至少一个采样时钟信号。
    • 7. 发明授权
    • Polar signal generator
    • 极地信号发生器
    • US08872596B2
    • 2014-10-28
    • US12304310
    • 2007-06-06
    • Manel Collados AsensioNenad PavlovicVojkan VidojkovicPaulus T. M. Van Zeijl
    • Manel Collados AsensioNenad PavlovicVojkan VidojkovicPaulus T. M. Van Zeijl
    • H03C3/38H03C5/00H03C3/40
    • H03C3/40H03C5/00
    • The present invention relates to a polar signal generator and method of deriving phase and amplitude components from in-phase (I) and quadrature-phase (Q) components of an input signal, wherein the I and Q components are generated at a first sampling frequency based on the input signal, and are then up-sampled in accordance with a predetermined first interpolation factor (N), to generate up-sampled I and Q components at a second sampling frequency higher than the first sampling frequency. The up-sampled I and Q components are converted into the phase and amplitude components, wherein the converting step is operated at the second sampling frequency. Moreover, the phase and amplitude components can be further up-sampled, optionally by different sampling frequencies, to a third and a fourth sampling frequency. Thereby, I-Q generation and cartesian-to-polar transformation can be performed at lower frequencies, which reduces power consumption.
    • 本发明涉及极性信号发生器和从输入信号的同相(I)和正交相(Q)分量中导出相位和幅度分量的方法,其中I和Q分量以第一采样频率 基于输入信号,然后根据预定的第一内插因子(N)进行上采样,以在高于第一采样频率的第二采样频率产生上采样的I和Q分量。 上采样的I和Q分量被转换成相位和幅度分量,其中转换步骤以第二采样频率运行。 此外,相位和幅度分量可以进一步上采样,可选地由不同的采样频率上升到第三和第四采样频率。 因此,可以以较低的频率执行I-Q生成和笛卡尔极坐标变换,这降低了功耗。
    • 9. 发明授权
    • Phase-to-frequency conversion for polar transmitters
    • 极性发射机的相对频率转换
    • US08086189B2
    • 2011-12-27
    • US12374491
    • 2007-06-19
    • Manel Collados AsensioNenad PavlovicVojkan VidojkovicPaulus T. M. Van Zeijl
    • Manel Collados AsensioNenad PavlovicVojkan VidojkovicPaulus T. M. Van Zeijl
    • H04B1/02H04L27/00
    • H04L27/361H03C5/00
    • The present invention relates to a polar transmission method and a polar transmitter for transmitting phase and amplitude components derived from in-phase (I) and quadrature-phase (Q) components of an input signal. A first conversion is provided for converting the in-phase (I) and quadrature-phase (Q) components into the phase and amplitude components at a first sampling rate. Additionally, a second conversion is provided for converting the phase component into a frequency component, wherein the second conversion comprises a rate conversion for converting the first sampling rate into a lower second sampling rate at which the frequency component is provided. Thereby, the second sampling rate can be used as a lower update rate in a digitally controlled oscillator in order to save power or because of speed limitations, while the surplus phase samples obtain due to the higher first sampling rate enable better approximation of the phase component after the digitally controlled oscillator. This better approximation accounts for a cleaner spectrum around the synthesized channel.
    • 本发明涉及一种用于发送从输入信号的同相(I)和正交相(Q)分量导出的相位和幅度分量的极性传输方法和极性发射器。 提供了第一转换,用于以第一采样率将同相(I)和正交相(Q)分量转换成相位和幅度分量。 另外,提供了将相位分量转换成频率分量的第二转换,其中第二转换包括用于将第一采样率转换成提供频率分量的较低第二采样率的速率转换。 因此,为了节省功率或由于速度限制,第二采样率可以用作数字控制振荡器中的较低更新速率,而由于较高的第一采样率而获得的剩余相位采样使得能够更好地近似相位分量 数字控制振荡器后。 这个更好的近似解释了合成通道周围更清晰的频谱。
    • 10. 发明申请
    • POLAR TRANSMITTER
    • 极性发射器
    • US20110164702A1
    • 2011-07-07
    • US13062330
    • 2009-08-24
    • Nenad PavlovicManel ColladosXin HeJan Van Sinderen
    • Nenad PavlovicManel ColladosXin HeJan Van Sinderen
    • H04L27/00
    • H04L27/361H04L27/2627H04L2027/0018H04L2027/0067
    • The present application relates to at least one digitally controlled oscillator and a data modulation device. More particularly, the digital polar transmitter comprises at least one digitally controlled oscillator configured to generate at least one frequency. The digital polar transmitter comprises a data modulation device, wherein the data modulation device comprises at least one data input terminal, at least one output terminal, and at least one frequency input terminal, wherein the output terminal is connected to the digitally controlled oscillator. The digital polar transmitter comprises a phase measuring device configured to measure phase information from the output signal of the data modulation device for every frequency sample. The digital polar transmitter comprises a phase error detecting device configured to detect a phase error at least depending on the measured phase information, wherein the phase error detecting device is configured to apply the detected phase error to the output signal of the data modulation device.
    • 本申请涉及至少一个数字控制振荡器和数据调制装置。 更具体地,数字极化发射器包括被配置为产生至少一个频率的至少一个数字控制振荡器。 数字极性发射机包括数据调制装置,其中数据调制装置包括至少一个数据输入端,至少一个输出端和至少一个频率输入端,其中输出端与数控振荡器相连。 数字极性发射机包括相位测量装置,其被配置为针对每个频率样本从数据调制装置的输出信号测量相位信息。 数字极性发射机包括相位误差检测装置,其被配置为至少根据所测量的相位信息检测相位误差,其中相位误差检测装置被配置为将检测到的相位误差应用于数据调制装置的输出信号。