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1. 发明授权

US08051121B2 Dual multiply-accumulator operation optimized for even and odd multisample calculations 有权
标题翻译：针对偶数和奇数多采样计算优化的双乘法累加器操作
公开(公告)号：US08051121B2
公开(公告)日：2011-11-01
申请号：US12042100
申请日：2008-03-04
申请人： Bradley C. Aldrich , Nigel C. Paver , William T. Maghielse
发明人： Bradley C. Aldrich , Nigel C. Paver , William T. Maghielse
IPC分类号： G06F17/10
CPC分类号： G06F7/5443 , G06F2207/3828
摘要： According to some embodiments, a dual multiply-accumulate operation optimized for even and odd multisample calculations is disclosed.
摘要翻译：根据一些实施例，公开了针对偶数和奇数多采样计算优化的双重乘法运算。

2. 发明授权

US07047393B2 Coprocessor processing instruction with coprocessor ID to broadcast main processor register data element to coprocessor multi-element register 有权
标题翻译：具有协处理器ID的协处理器处理指令，以将主处理器寄存器数据元件广播到协处理器多元件寄存器
公开(公告)号：US07047393B2
公开(公告)日：2006-05-16
申请号：US10263246
申请日：2002-10-02
申请人： Nigel C. Paver , Wing K. Yu , Murli Ganeshan
发明人： Nigel C. Paver , Wing K. Yu , Murli Ganeshan
IPC分类号： G06F9/315
CPC分类号： G06F9/30181 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30072 , G06F9/30094 , G06F9/30101 , G06F9/30112 , G06F9/30145 , G06F9/3816 , G06F9/3824 , G06F9/3842 , G06F9/3877 , G06F9/3879 , G06F9/3885
摘要： A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type. A source register in the main processor and a destination register is in the coprocessor, those registers including data elements. The coprocessor instruction includes an opcode specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for the coprocessor instruction, the instruction to broadcast a data element from said source register to said destination register.
摘要翻译：基于处理器的系统可以包括主处理器和协处理器。协处理器处理包括指定要由协处理器执行的数据处理操作的操作码的指令和用于识别用于协处理器指令的目标协处理器的协处理器标识字段。两位表示四个数据大小之一，包括一个字节（8位），一个半字（16位），一个字（32位）和一个双字（64位）。另外两个位表示饱和类型。主处理器中的源寄存器和目标寄存器位于协处理器中，这些寄存器包括数据元素。协处理器指令包括指定由协处理器执行的数据处理操作的操作码和用于识别用于协处理器指令的目标协处理器的协处理器识别字段，将数据元素从所述源寄存器广播到所述目的地寄存器的指令。

3. 发明授权

US08725953B2 Local cache power control within a multiprocessor system 有权
标题翻译：多处理器系统内的本地缓存功率控制
公开(公告)号：US08725953B2
公开(公告)日：2014-05-13
申请号：US12320211
申请日：2009-01-21
申请人： Nigel C Paver , Stuart D Biles , Kevin P Welton , Paul G Meyer
发明人： Nigel C Paver , Stuart D Biles , Kevin P Welton , Paul G Meyer
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0831 , G06F12/0891 , G06F2212/1028 , Y02D10/13
摘要： A data processing system including a plurality of processors 4, 6, 8 each having a local cache memory 10, 12, 14 is provided. A cache coherency controller 16 serves to maintain cache coherency between the local cache memories 10, 12, 14. When one of the processors 4, 6, 8 is placed into a low power state its associated local cache memory 10, 12, 14 is maintained in a state in which the data it is holding is accessible to the cache coherency controller 16 until a predetermined condition has been met whereupon the local cache memory 10, 12, 14 concerned is placed into a low power state. The predetermined condition can take a variety of different forms such as the rate of snoop hits falling below a threshold value, the ratio of snooping hits to snoop requests falling below a threshold value, a predetermined number of clock cycles passing since the associated processor for that local cache memory was powered down as well as other possibilities.
摘要翻译：提供了包括多个具有本地高速缓冲存储器10,12,14的处理器4,6,8的数据处理系统。高速缓存一致性控制器16用于维持本地高速缓存存储器10,12,14之间的高速缓存一致性。当处理器4,6,8中的一个被置于低功率状态时，其相关的本地高速缓冲存储器10,12,14被维持在高速缓存一致性控制器16可访问其所保存的数据的状态下，直到满足预定条件，然后将有关的本地高速缓冲存储器10,12,14置于低功率状态。预定条件可以采取各种不同的形式，例如，窥探命中率低于阈值，侦听命中与窥探请求的比率低于阈值，从相关联的处理器通过的预定数量的时钟周期本地缓存内存已被掉电以及其他可能性。

4. 发明申请

US20120057801A1 Residual Addition for Video Software Techniques 有权
标题翻译：视频软件技术的剩余加法
公开(公告)号：US20120057801A1
公开(公告)日：2012-03-08
申请号：US13296759
申请日：2011-11-15
申请人： Bradley C. Aldrich , Nigel C. Paver , Murli Ganeshan
发明人： Bradley C. Aldrich , Nigel C. Paver , Murli Ganeshan
IPC分类号： G06K9/36
CPC分类号： G06F9/3001 , G06F9/30036 , H04N19/42 , H04N19/43 , H04N19/436 , H04N19/44
摘要： According to some embodiments, a technique provides for the execution of an instruction that includes receiving residual data of a first image and decoded pixels of a second image, zero-extending a plurality of unsigned data operands of the decoded pixels producing a plurality of unpacked data operands, adding a plurality of signed data operands of the residual data to the plurality of unpacked data operands producing a plurality of signed results; and saturating the plurality of signed results producing a plurality of unsigned results.
摘要翻译：根据一些实施例，一种技术提供了一种指令的执行，该指令包括接收第一图像的残差数据和第二图像的解码像素，零扩展解码像素的多个无符号数据操作数，产生多个未打包数据操作数，将剩余数据的多个有符号数据操作数添加到产生多个签名结果的多个未打包数据操作数; 并且产生多个无符号结果的多个签名结果饱和。

5. 发明授权

US07373488B2 Processing for associated data size saturation flag history stored in SIMD coprocessor register using mask and test values 有权
标题翻译：使用掩码和测试值处理存储在SIMD协处理器寄存器中的相关数据大小饱和标志历史记录
公开(公告)号：US07373488B2
公开(公告)日：2008-05-13
申请号：US11797067
申请日：2007-04-30
申请人： Nigel C. Paver , Bradley C. Aldrich
发明人： Nigel C. Paver , Bradley C. Aldrich
IPC分类号： G06F9/305
CPC分类号： G06F9/30181 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30072 , G06F9/30094 , G06F9/30101 , G06F9/30112 , G06F9/30145 , G06F9/3816 , G06F9/3824 , G06F9/3842 , G06F9/3877 , G06F9/3879 , G06F9/3885
摘要： A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information. A first coprocessor instruction has a first format identifying a saturating operation, a first source having packed data elements and a second source having packed data elements. The saturating operation is executed on the packed data elements of the first and second sources. Saturation flags are stored in the Wireless Coprocessor Saturation Status Flag (wCSSF) register to indicate if a result of the saturating operation saturated. A second coprocessor instruction has a second format identifying a saturation history processing operation and a saturation data size. An operand for the processing operation is determined based on the saturation data size, and the processing operation is executed on the saturation flags and the operand for the saturation data size. Condition code flags are stored in a status register to indicate the result of processing operation.
摘要翻译：一种用于计算和存储单指令多数据（SIMD）饱和历史信息的方法和装置。第一协处理器指令具有标识饱和操作的第一格式，具有打包数据元素的第一源和具有打包数据元素的第二源。对第一和第二源的压缩数据元素执行饱和操作。饱和标志存储在无线协处理器饱和状态标志（wCSSF）寄存器中，以指示饱和操作的结果是否饱和。第二协处理器指令具有标识饱和历史处理操作和饱和度数据大小的第二格式。基于饱和度数据大小确定处理操作的操作数，并且对饱和度标志和饱和度数据大小的操作数执行处理操作。条件码标志存储在状态寄存器中，以指示处理操作的结果。

6. 发明授权

US07245945B2 Portable computing device adapted to update display information while in a low power mode 有权
标题翻译：适于在低功率模式下更新显示信息的便携式计算设备
公开(公告)号：US07245945B2
公开(公告)日：2007-07-17
申请号：US10289081
申请日：2002-11-05
申请人： Nigel C. Paver , Mark Fullerton
发明人： Nigel C. Paver , Mark Fullerton
IPC分类号： H04B1/38 , G01R31/08
CPC分类号： G09G5/363 , G06F1/3203 , G09G2330/021 , H04W52/0209 , Y02D70/1224 , Y02D70/124 , Y02D70/142 , Y02D70/144
摘要： Briefly, in accordance with one embodiment of the invention, a portable computing device that has a processor, a direct memory access (DMA) engine, and a display controller may transfer data with the DMA engine to the display. The DMA engine may transfer the data while the processor is in a standby mode and transfer data to the processor while the processor is executing instructions.
摘要翻译：简而言之，根据本发明的一个实施例，具有处理器，直接存储器访问（DMA）引擎和显示控制器的便携式计算设备可以将DMA引擎的数据传送到显示器。当处理器处于待机模式时，DMA引擎可以传输数据，并在处理器执行指令时将数据传输到处理器。

7. 发明授权

US07035331B2 Method and apparatus for performing a pixel averaging instruction 有权
标题翻译：用于执行像素平均指令的方法和装置
公开(公告)号：US07035331B2
公开(公告)日：2006-04-25
申请号：US10081926
申请日：2002-02-20
申请人： Yuyun Liao , Nigel C. Paver , James E. Quinlan
发明人： Yuyun Liao , Nigel C. Paver , James E. Quinlan
IPC分类号： H04N7/12 , H04N11/02
CPC分类号： G06F17/18 , G06F7/49947 , G06F7/509 , G06F7/544 , G06F2207/3828 , G06T1/20 , G06T2200/28
摘要： In an embodiment, a functional unit including a compressor section and a 36-bit SIMD adder is used to perform a STMD four-pixel averaging instruction. The functional unit generates four four-pixel averages. Four pixel values and a rounding value are compressed into a sum and a carry vector. The two least significant bits of the sum vector and the LSB of the carry vector are dropped before being input to the 36-bit SIMD adder. The two resultant 8-bit vectors are added by the 36-bit adder to directly generate the average pixel value result.
摘要翻译：在一个实施例中，使用包括压缩器部分和36位SIMD加法器的功能单元来执行SIMD四像素平均指令。功能单元产生四个四像素平均值。四个像素值和舍入值被压缩为和和进位向量。和矢量的两个最低有效位和进位向量的LSB在输入到36位SIMD加法器之前被丢弃。两个结果的8位向量由36位加法器相加，以直接生成平均像素值结果。

8. 发明授权

US06055620A Apparatus and method for system control using a self-timed asynchronous control structure 失效
标题翻译：使用自定时异步控制结构进行系统控制的装置和方法
公开(公告)号：US06055620A
公开(公告)日：2000-04-25
申请号：US932956
申请日：1997-09-18
申请人： Nigel C. Paver , Paul Day
发明人： Nigel C. Paver , Paul Day
IPC分类号： G06F9/318 , G06F9/38 , G06F5/00
CPC分类号： G06F9/3871 , G06F9/30181 , G06F9/3842 , G06F9/3867
摘要： A control apparatus and method is provided for controlling operations of functional units in systems. The control apparatus and method implement a set of operations that can include dependencies between the functional units of a system to complete each operation. For example, in an asynchronous digital processor, self-timing and inter-block communication are used to implement a self-timed scheduler. The self-timed scheduler and method implement an instruction set using a plurality of functional units of the asynchronous digital processor. A scheduler can include a scheduler decoder that decodes each instruction to generate functional unit schedule and control information, a communication device and a plurality of scheduler functional unit controllers, wherein each of the scheduler functional unit controllers corresponds to one of the plurality of functional units of a system.
摘要翻译：提供一种用于控制系统中的功能单元的操作的控制装置和方法。控制装置和方法实现一组操作，其可以包括系统的功能单元之间的依赖关系以完成每个操作。例如，在异步数字处理器中，使用自定时和块间通信来实现自定时调度器。自定时调度器和方法使用异步数字处理器的多个功能单元来实现指令集。调度器可以包括解码每个指令以生成功能单元调度和控制信息的调度器解码器，通信设备和多个调度器功能单元控制器，其中每个调度器功能单元控制器对应于多个功能单元中的一个一个系统。

9. 发明授权

US5574925A Asynchronous pipeline having condition detection among stages in the pipeline 失效
标题翻译：异步管道在管道中的各个阶段之间具有条件检测
公开(公告)号：US5574925A
公开(公告)日：1996-11-12
申请号：US182191
申请日：1994-01-19
申请人： Nigel C. Paver
发明人： Nigel C. Paver
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3871 , G06F9/30141
摘要： A condition detector for an asynchronous pipeline. Each stage in the pipeline includes a storage element for storing a single bit of data indicating whether or not the condition to be detected is set in that stage. The single bit in the storage element of one stage is transferred to the storage element of a succeeding stage in the pipeline when data is transferred between those stages. A detector detects whether or not any one of the storage elements of the pipeline stages indicates that the condition is set, and a condition set output is generated if any one of the storage elements of the pipeline stages indicates that the condition is set.
摘要翻译： PCT No.PCT / GB92 / 00959 Sec。 371日期1994年1月19日 102（e）日期1994年1月19日PCT提交1992年5月27日PCT公布。第WO93 / 01544号公报日期1993年1月21日用于异步管道的状态检测器。流水线中的每个阶段包括用于存储指示在该阶段是否设置待检测条件的单位数据的存储元件。当数据在这些级之间传送时，一级存储元件中的单个位被传送到流水线中的后续级的存储元件。检测器检测流水线级的任何一个存储元件是否指示条件被设置，并且如果流水线级的任何一个存储元件指示条件被设置，则产生条件集输出。

10. 发明授权

US08756267B1 Dual-multiply-accumulator operation optimized for even and odd multisample calculations 有权
标题翻译：针对偶数和奇数多样本计算优化的双乘法累加器操作
公开(公告)号：US08756267B1
公开(公告)日：2014-06-17
申请号：US13285830
申请日：2011-10-31
申请人： Bradley Aldrich , Nigel C. Paver , William T. Maghielse
发明人： Bradley Aldrich , Nigel C. Paver , William T. Maghielse
IPC分类号： G06F17/10
CPC分类号： G06F7/5443 , G06F2207/3828
摘要： According to some embodiments, a device is configured to perform a dual multiply-accumulate operation. In one embodiment, the device includes a functional unit configured to calculate, in parallel, a first multiplication product of a first coefficient and a first sample; and a second multiplication product of the first coefficient and a second sample. The first sample is an (n)th sample and the second sample is an (n+2)th sample in a plurality of sequential samples. The functional unit outputs and stores the first multiplication product and the second multiplication product in different storage locations in at least one storage device.
摘要翻译：根据一些实施例，设备被配置为执行双乘法累加操作。在一个实施例中，设备包括功能单元，其被配置为并行计算第一系数和第一样本的第一乘积; 以及第一系数和第二样本的第二乘积。第一样本是第（n）个样本，第二样本是多个顺序样本中的第（n + 2）个样本。功能单元将至少一个存储设备中的第一乘法乘积和第二乘法乘积存储在不同的存储位置中。

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