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    • 7. 发明授权
    • Broadband any point to any point switch matrix
    • 宽带任何点到任何点开关矩阵
    • US06205138B1
    • 2001-03-20
    • US09066209
    • 1998-04-24
    • Perwaiz NihalRobert Alan FlavinThompson Baum VeseckyNorbert George VoglEdward Payson Clarke, Jr.Luis Rodriguez-CortesGeoffrey Hale Purdy
    • Perwaiz NihalRobert Alan FlavinThompson Baum VeseckyNorbert George VoglEdward Payson Clarke, Jr.Luis Rodriguez-CortesGeoffrey Hale Purdy
    • H04L1250
    • H04L49/101H04L49/201H04L49/351H04L49/40
    • This invention is a broadband matrix switch system and method of operation. The broadband matrix switch has N number of broadband inputs, each of the broadband inputs having one or more broadband signals. The matrix switch has M number of broadband outputs. There are N number of splitters. Each of the splitters has a splitter input connected to one of the broadband inputs. Each of the splitters has M number of splitter outputs that produce the splitter output signal. There are N times M number of node switches. Each node switch is uniquely connected to one of the splitter outputs. The node switches have a control input that allows the node switch to pass the respective splitter output signal upon receiving a close command at the control input and to terminate the respective splitter output signal with an input impedance upon receiving an open command at the control input. There are M number of combiners. Each combiner has a combiner output connected to one of the broadband outputs. Each combiner further having N number of combiner inputs. Each of the combiner inputs are connected to one and only one of the inputs through the respective splitter and node switch. The node switches terminate the combiner input with an output impedance upon receiving an open command. The matrix switch further has a controller that sends one or more open commands to selected node switches to connect one or more of the broadband inputs to one or more of the broadband outputs. The matrix switch has many uses in switching and monitoring and analyzing broadband networks, for example, cable TV networks.
    • 本发明是宽带矩阵切换系统及其操作方法。 宽带矩阵切换器具有N个宽带输入,每个宽带输入具有一个或多个宽带信号。 矩阵开关具有M个宽带输出。 有N个分割器。 每个分路器具有连接到一个宽带输入的分路器输入。 每个分路器具有M个分路器输出,产生分路器输出信号。 有N次M个节点交换机。 每个节点开关独特地连接到分路器输出之一。 节点开关具有控制输入,其允许节点开关在接收到控制输入端的关闭命令时通过相应的分离器输出信号,并且在控制输入端接收到打开命令时终止具有输入阻抗的相应分离器输出信号。 有M个组合器。 每个组合器具有连接到其中一个宽带输出的组合器输出。 每个组合器还具有N个组合器输入。 每个组合器输入通过相应的分离器和节点开关连接到一个且仅一个输入。 节点开关在接收到打开命令时终止具有输出阻抗的组合器输入。 矩阵开关还具有控制器,该控制器向所选择的节点开关发送一个或多个打开的命令,以将一个或多个宽带输入连接到一个或多个宽带输出。 矩阵开关在切换和监测和分析宽带网络方面有许多用途,例如有线电视网络。
    • 8. 发明授权
    • Twin nodes capacitance memory
    • 双电源电容存储器
    • US4040016A
    • 1977-08-02
    • US672196
    • 1976-03-31
    • Hsing-San LeeNorbert George Vogl, Jr.
    • Hsing-San LeeNorbert George Vogl, Jr.
    • G11C11/405G11C11/24G11C11/35H01L21/8242H01L27/10H01L27/108G11C11/40
    • H01L27/108G11C11/24G11C11/35
    • A semiconductor memory produced in a unipolar technology includes a cell which has a pair of inversion capacitors with one terminal of each capacitor connected to one of a pair of bit/sense lines, the other terminal of each capacitor is coupled to a source of charges by a pulse from a word line. The charges produced from the source may be in the form of pulses injected into the capacitors. To provide a word organized array of these cells, each word includes a source of charges produced at the surface of a semiconductor substrate and a plurality of pairs of inversion capacitors formed also at the surface of the semiconductor in spaced apart relationship from the charge source. Information is written into the pairs of capacitors by applying complementary voltages to each pair of bit/sense lines coupled to the pairs of capacitors while a word pulse produces inversion layers at the surface of the substrate between the capacitors to interconnect serially the charge source with each of the capacitors. The complementary voltages have a first and a second magnitude. When voltages of the first and second magnitudes are applied to first and second bit/sense lines, respectively, of a pair of bit/sense lines, a 1 bit of information is stored in the associated cell, and when voltages of the second and first magnitudes are applied to the first and second bit/sense lines, respectively, of the same pair of bit/sense lines, a 0 bit of information is stored in the associated cell. The capacitor of the pair of capacitors having the larger voltage applied thereto stores the greater amount of charge. By employing a differential sense amplifier and floating the pair of bit sense line when a word pulse again connects the charge source with each of the capacitors, the greater charge can be detected by noting the polarity of the different voltage between the two capacitors of the pair of capacitors.