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1. 发明授权

US09379180B2 Super junction for semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置用超级结及其制造方法
公开(公告)号：US09379180B2
公开(公告)日：2016-06-28
申请号：US14104525
申请日：2013-12-12
申请人： PFC Device Holdings Limited
发明人： Paul Chung-Chen Chang , Kuo-Liang Chao , Mei-Ling Chen , Lung-Ching Kao
IPC分类号： H01L29/06 , H01L21/266 , H01L21/265 , H01L21/324 , H01L29/08 , H01L29/66 , H01L29/739 , H01L29/74 , H01L29/861 , H01L29/872 , H01L29/78 , H01L29/749
CPC分类号： H01L29/0634 , H01L21/26513 , H01L21/266 , H01L21/324 , H01L29/0878 , H01L29/66136 , H01L29/66143 , H01L29/66333 , H01L29/66363 , H01L29/66712 , H01L29/7393 , H01L29/74 , H01L29/749 , H01L29/7802 , H01L29/861 , H01L29/872
摘要： A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.
摘要翻译：用于半导体器件的超结包括具有第一导电类型外延层的硅衬底，以及形成在第一导电型外延层中的多个高度掺杂的第二导电型列，以及多个轻掺杂（第一导电类型或第二导电型）侧壁形成在高掺杂的第二导电类型的外表面上。半导体器件是超结MOSFET，超结MOSFET，超结肖特基整流器，超结IGBT，晶闸管或超结二极管。

2. 发明授权

US09520479B1 Low-temperature epitaxial method for manufacturing backside field stop layer of insulated gate bipolar transistor (IGBT) 有权
标题翻译：用于制造绝缘栅双极晶体管（IGBT）的背面场停止层的低温外延法
公开(公告)号：US09520479B1
公开(公告)日：2016-12-13
申请号：US15046294
申请日：2016-02-17
申请人： PFC Device Holdings Limited
发明人： Mei-Ling Chen , Kuan-Yu Chen
IPC分类号： H01L21/332 , H01L29/66 , H01L29/417 , H01L21/02
CPC分类号： H01L29/66333 , H01L29/36 , H01L29/7395
摘要： A low-temperature epitaxial method manufactures backside field stop layer of insulated gate bipolar transistor (IGBT) first provides a first conductive type substrate and fabricates front-side elements and front metal layer on a front side of the IGBT. A second conductive type impurity layer is formed on a back side of the first conductive type substrate by low-temperature epitaxial process and a collector metal layer is formed on bottom face of the first conductive type substrate.
摘要翻译：制造绝缘栅双极晶体管（IGBT）的背面场停止层的低温外延法首先提供第一导电型衬底，并在IGBT的前侧制造前侧元件和前金属层。通过低温外延法在第一导电类型基板的背面上形成第二导电类型杂质层，并且在第一导电型基板的底面上形成集电极金属层。

3. 发明授权

US09455328B1 Low-temperature oxide method for manufacturing backside field stop layer of insulated gate bipolar transistor 有权
标题翻译：用于制造绝缘栅双极晶体管的背面场停止层的低温氧化物方法
公开(公告)号：US09455328B1
公开(公告)日：2016-09-27
申请号：US15046334
申请日：2016-02-17
申请人： PFC Device Holdings Limited
发明人： Kuan-Yu Chen , Mei-Ling Chen
IPC分类号： H01L21/332 , H01L29/66 , H01L29/06 , H01L21/02 , H01L21/308
CPC分类号： H01L29/66333 , H01L21/041 , H01L21/0485 , H01L29/0615 , H01L29/0834 , H01L29/36 , H01L29/456 , H01L29/7395
摘要： A low-temperature oxide method is used for manufacturing backside field stop layer of IGBT and first fabricates front elements and front metal layer on a first face of a first conductive type substrate. A multiple-recesses structure is formed on a back side of the first conductive type substrate. Each of the recess in the multiple-recesses structure has first conductive type implanted patterns on exterior sides thereof and the multiple-recesses structure has a first conductive type implanted layer on bottom thereof. A plurality of first conductive type polysilicon layers are deposited into the multiple-recesses structure and respectively corresponding to the first conductive type implanted patterns. A second conductive type impurity layer is formed on the bottom of the first conductive type substrate and laser annealing is conducted to form backside field stop layer for IGBT.
摘要翻译：使用低温氧化法制造IGBT的背面场阻挡层，并且首先在第一导电型衬底的第一面上制造前元件和前金属层。多凹部结构形成在第一导电型基板的背面上。多凹部结构中的每个凹部在其外侧上具有第一导电型植入图案，并且多凹部结构在其底部具有第一导电型注入层。多个第一导电型多晶硅层沉积到多凹槽结构中并且分别对应于第一导电型植入图案。在第一导电型基板的底部形成第二导电型杂质层，并进行激光退火以形成用于IGBT的背面场停止层。

4. 发明申请

US20140167205A1 SUPER JUNCTION FOR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：用于半导体器件的超级连接及其制造方法
公开(公告)号：US20140167205A1
公开(公告)日：2014-06-19
申请号：US14104525
申请日：2013-12-12
申请人： PFC DEVICE HOLDINGS LIMITED
发明人： Paul Chung-Chen CHANG , Kuo-Liang CHAO , Mei-Ling CHEN , Lung-Ching KAO
IPC分类号： H01L29/06
CPC分类号： H01L29/0634 , H01L21/26513 , H01L21/266 , H01L21/324 , H01L29/0878 , H01L29/66136 , H01L29/66143 , H01L29/66333 , H01L29/66363 , H01L29/66712 , H01L29/7393 , H01L29/74 , H01L29/749 , H01L29/7802 , H01L29/861 , H01L29/872
摘要： A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.
摘要翻译：用于半导体器件的超结包括具有第一导电类型外延层的硅衬底，以及形成在第一导电型外延层中的多个高度掺杂的第二导电型列，以及多个轻掺杂（第一导电类型或第二导电型）侧壁形成在高掺杂的第二导电类型的外表面上。半导体器件是超结MOSFET，超结MOSFET，超结肖特基整流器，超结IGBT，晶闸管或超结二极管。

5. 发明申请

US20170148889A1 METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR POWER DEVICE WITH MULTI GATES CONNECTION 审中-公开
公开(公告)号：US20170148889A1
公开(公告)日：2017-05-25
申请号：US15057931
申请日：2016-03-01
申请人： PFC Device Holdings Limited
发明人： Kuan-Yu CHEN , Hsu-Heng LI , Mei-Ling CHEN
IPC分类号： H01L29/49 , H01L21/28 , H01L29/06 , H01L29/78 , H01L29/66
CPC分类号： H01L29/4925 , H01L28/00 , H01L29/40114 , H01L29/407 , H01L29/41766 , H01L29/66484 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/7831
摘要： A metal oxide semiconductor field effect transistor (MOSFET) power device with multi gates connection includes a first-conductive type substrate, a first-conductive type epitaxial layer arranged on the first-conductive type substrate, a plurality of device trenches defined on an upper face of the first-conductive type epitaxial layer. Each of the device trenches has, from bottom of the trench to top of the trench, a bottom gate, a split gate and a trench gate. A bottom insulating layer is formed between the bottom gate and the bottom of the trench, an intermediate insulating layer is formed between the bottom gate and the split gate, an upper insulating layer is formed between the split gate and the trench gate.

6. 发明授权

US09373728B2 Trench MOS PN junction diode structure 有权
标题翻译：沟槽MOS PN结二极管结构
公开(公告)号：US09373728B2
公开(公告)日：2016-06-21
申请号：US14537280
申请日：2014-11-10
申请人： PFC Device Holdings Limited
发明人： Mei-Ling Chen
IPC分类号： H01L29/861 , H01L29/06 , H01L29/66 , H01L21/265 , H01L21/3205 , H01L29/40
CPC分类号： H01L29/861 , H01L21/265 , H01L21/32055 , H01L29/0619 , H01L29/0623 , H01L29/407 , H01L29/66136
摘要： A trench MOS PN junction diode structure includes a first conductive type substrate, a plurality of trenches defined on a face of the first conductive type substrate, a gate oxide layer formed at least on inner sidewalls of the trenches, a polysilicon layer formed in the trenches, a second conductive type low-concentration ion-implanted region formed at least in the first conductive type substrate, a high-concentration ion-implanted region formed below the trenches, and an electrode layer covering the first conductive type substrate, the second conductive type low-concentration ion-implanted region, the gate oxide and the polysilicon layer. The high-concentration ion-implanted region below the trenches provides pinch-off voltage sustention in reversed bias operation to reduce leakage current of the trench MOS PN junction diode structure.
摘要翻译：沟槽MOS PN结二极管结构包括第一导电型衬底，限定在第一导电类型衬底的表面上的多个沟槽，至少形成在沟槽的内侧壁上的栅极氧化层，形成在沟槽中的多晶硅层至少形成在第一导电型基板中的第二导电型低浓度离子注入区域，形成在沟槽下方的高浓度离子注入区域和覆盖第一导电型基板的电极层，第二导电型低浓度离子注入区域，栅极氧化物和多晶硅层。沟槽下方的高浓度离子注入区域在反向偏置操作中提供了夹断电压，以减少沟槽MOS PN结二极管结构的漏电流。

7. 发明申请

US20150279980A1 HIGH-PERFORMANCE REVERSE-CONDUCTION FIELD-STOP (RCFS) INSULATED GATE BIPOLAR TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：高性能反向导通现场停止（RCFS）绝缘栅双极晶体管及其制造方法
公开(公告)号：US20150279980A1
公开(公告)日：2015-10-01
申请号：US14526090
申请日：2014-10-28
申请人： PFC Device Holdings Limited
发明人： Mei-Ling CHEN , Hung-Hsin KUO , Yi-Lun HSIA , Chung-Chen CHANG
IPC分类号： H01L29/739 , H01L21/324 , H01L21/762 , H01L29/66 , H01L21/265
CPC分类号： H01L29/7396 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L21/76224 , H01L29/0834 , H01L29/66333
摘要： A high-performance reverse-conduction field-stop (RCFS) insulated gate bipolar transistor (IGBT) includes a first conductive type substrate, a plurality of trenches defined on a bottom face of the substrate, a plurality of first conductive type doping regions formed on bottom face of the trenches, a second conductive type doping region formed on bottom face of the substrate, and a first conductive type field stop doping region formed in the substrate and separated from the bottom face of the substrate by a field stop depth, where the field stop depth is larger than a depth of the trench. Due to a separation between the first conductive type doping regions and the second conductive type doping region, Zener diode can be prevented from forming on bottom side of the substrate and the performance of IGBT can be accordingly enhanced.
摘要翻译：高性能反向导通场停止（RCFS）绝缘栅双极晶体管（IGBT）包括：第一导电型衬底，限定在衬底的底面上的多个沟槽;多个第一导电型掺杂区，形成在沟槽的底面，形成在基板的底面上的第二导电型掺杂区域和形成在基板中并且通过场停止深度从基板的底面分离的第一导电型场阻止掺杂区域，其中场停止深度大于沟槽的深度。由于第一导电型掺杂区域和第二导电型掺杂区域之间的分离，可以防止齐纳二极管在衬底的底侧形成，并且可以相应地提高IGBT的性能。

8. 发明申请

US20190355810A1 SEMICONDUCTOR DEVICE WITH SUPER JUNCTION AND PROCESS FOR THE SAME 审中-公开
公开(公告)号：US20190355810A1
公开(公告)日：2019-11-21
申请号：US16048628
申请日：2018-07-30
申请人： PFC Device Holdings Limited
发明人： Kuan-Yu CHEN
IPC分类号： H01L29/06 , H01L21/265 , H01L21/266 , H01L29/167 , H01L29/08 , H01L29/10
摘要： A semiconductor device with super junction and process for the same is disclosed. The semiconductor device includes a silicon substrate and a first conductive type epitaxial layer thereon, a plurality of second conductive type conductive pillars formed below an upper face of the first conductive type epitaxial layer, where the second conductive type conductive pillars are implanted with neutral element having predetermined amount. When the semiconductor device operates in a predetermined temperature, the releasing amount of the neutral element can completely or partially compensate the releasing amount of carrier of opposite polarity from the epitaxial layer for the second conductive type conductive pillars due to the predetermined temperature, thus prevent the degrade of endurance ability for the surge voltage.

9. 发明授权

US09406745B2 Method of manufacturing super junction for semiconductor device 有权
标题翻译：制造半导体器件超导结的方法
公开(公告)号：US09406745B2
公开(公告)日：2016-08-02
申请号：US14807242
申请日：2015-07-23
申请人： PFC Device Holdings Limited
发明人： Paul Chung-Chen Chang , Kuo-Liang Chao , Mei-Ling Chen , Lung-Ching Kao
IPC分类号： H01L21/20 , H01L29/06 , H01L21/266 , H01L21/265 , H01L21/324 , H01L29/08 , H01L29/66 , H01L29/739 , H01L29/74 , H01L29/861 , H01L29/872 , H01L29/78 , H01L29/749
CPC分类号： H01L29/0634 , H01L21/26513 , H01L21/266 , H01L21/324 , H01L29/0878 , H01L29/66136 , H01L29/66143 , H01L29/66333 , H01L29/66363 , H01L29/66712 , H01L29/7393 , H01L29/74 , H01L29/749 , H01L29/7802 , H01L29/861 , H01L29/872
摘要： A method of manufacturing super junction for semiconductor device is disclosed. The super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.
摘要翻译：公开了半导体器件的超结的制造方法。用于半导体器件的超结包括具有第一导电类型外延层的硅衬底和形成在第一导电型外延层中的多个高度掺杂的第二导电型列，以及多个轻掺杂（第一导电类型或第二导电型）侧壁形成在高掺杂的第二导电类型的外表面上。半导体器件是超结MOSFET，超结MOSFET，超结肖特基整流器，超结IGBT，晶闸管或超结二极管。

10. 发明授权

US09240470B2 High-performance reverse-conduction field-stop (RCFS) insulated gate bipolar transistor and method for manufacturing the same 有权
标题翻译：高性能反向导通场停止（RCFS）绝缘栅双极晶体管及其制造方法
公开(公告)号：US09240470B2
公开(公告)日：2016-01-19
申请号：US14526090
申请日：2014-10-28
申请人： PFC Device Holdings Limited
发明人： Mei-Ling Chen , Hung-Hsin Kuo , Yi-Lun Hsia , Chung-Chen Chang
IPC分类号： H01L29/06 , H01L29/739 , H01L29/66 , H01L21/265 , H01L21/762 , H01L21/324
CPC分类号： H01L29/7396 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L21/76224 , H01L29/0834 , H01L29/66333
摘要： A high-performance reverse-conduction field-stop (RCFS) insulated gate bipolar transistor (IGBT) includes a first conductive type substrate, a plurality of trenches defined on a bottom face of the substrate, a plurality of first conductive type doping regions formed on bottom face of the trenches, a second conductive type doping region formed on bottom face of the substrate, and a first conductive type field stop doping region formed in the substrate and separated from the bottom face of the substrate by a field stop depth, where the field stop depth is larger than a depth of the trench. Due to a separation between the first conductive type doping regions and the second conductive type doping region, Zener diode can be prevented from forming on bottom side of the substrate and the performance of IGBT can be accordingly enhanced.
摘要翻译：高性能反向导通场停止（RCFS）绝缘栅双极晶体管（IGBT）包括：第一导电型衬底，限定在衬底的底面上的多个沟槽;多个第一导电型掺杂区，形成在沟槽的底面，形成在基板的底面上的第二导电型掺杂区域和形成在基板中并且通过场停止深度从基板的底面分离的第一导电型场阻止掺杂区域，其中场停止深度大于沟槽的深度。由于第一导电型掺杂区域和第二导电型掺杂区域之间的分离，可以防止齐纳二极管在衬底的底侧形成，并且可以相应地提高IGBT的性能。

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