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1. 发明授权

US08779596B2 Structures and methods to enhance copper metallization 有权
标题翻译：增强铜金属化的结构和方法
公开(公告)号：US08779596B2
公开(公告)日：2014-07-15
申请号：US10854552
申请日：2004-05-26
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L23/48
CPC分类号： H01L21/76841 , H01L21/32051 , H01L21/76814 , H01L21/76823 , H01L21/76825 , H01L21/76828 , H01L21/76831 , H01L21/76843 , H01L21/76855 , H01L21/76859 , H01L21/76867 , H01L21/76873 , H01L21/76874 , H01L21/76879 , H01L21/7688 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator includes a polymer or an insulating oxide compound. And, the inhibiting layer has a compound formed from a reaction between the polymer or insulating oxide compound and a transition metal, a representative metal, or a metalloid.
摘要翻译：公开的结构和方法抑制半导体结构中的金属化层和绝缘体层之间的原子迁移和相关的电容 - 电阻效应。一个示例性结构包括绝缘体和金属化层之间的抑制层。绝缘体包括聚合物或绝缘氧化物化合物。并且，抑制层具有由聚合物或绝缘氧化物化合物与过渡金属，代表性金属或准金属之间的反应形成的化合物。

2. 发明授权

US08592964B2 Apparatus and method for high density multi-chip structures 有权
公开(公告)号：US08592964B2
公开(公告)日：2013-11-26
申请号：US11458859
申请日：2006-07-20
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L23/34
CPC分类号： H01L23/5226 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2924/0002 , H01L2924/00
摘要： Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection structures and through chip connection structures. One advantage of this design includes an increased number of possible connections. Another advantage of this design includes shorter distances for interconnection pathways, which improves device performance and speed.

3. 发明申请

US20130001575A1 METHODS FOR STRESSING TRANSISTOR CHANNELS OF A SEMICONDUCTOR DEVICE STRUCTURE, AND A RELATED SEMICONDUCTOR DEVICE STRUCTURE 有权
标题翻译：用于压制半导体器件结构的晶体管通道的方法和相关的半导体器件结构
公开(公告)号：US20130001575A1
公开(公告)日：2013-01-03
申请号：US13611249
申请日：2012-09-12
申请人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
发明人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7833 , B82Y10/00 , H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L29/66492 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.
摘要翻译：本发明包括用于应力半导体器件结构的晶体管沟道的方法。这种方法包括形成邻近源极/漏极区域的所谓近表面纳米孔，形成邻近并包括纳米孔的源极/漏极区域的延伸部分，以及将扩大或收缩体积的类型的植入物质分别取决于在NMOS场效应晶体管中如在NMOS场效应晶体管中在纳米腔中的晶体管通道中是否需要压缩应变，如在PMOS场效应晶体管中的拉伸应变或拉伸应变，以增强载流子迁移率和晶体管速度。还公开了包括这些特征的半导体器件结构和半导体器件。

4. 发明申请

US20120302006A1 DISTRIBUTED SEMICONDUCTOR DEVICE METHODS, APPARATUS, AND SYSTEMS 有权
标题翻译：分布式半导体器件方法，设备和系统
公开(公告)号：US20120302006A1
公开(公告)日：2012-11-29
申请号：US13567839
申请日：2012-08-06
申请人： Paul A. Farrar , Hussein I. Hanafi
发明人： Paul A. Farrar , Hussein I. Hanafi
IPC分类号： H01L21/50 , H01L21/768
CPC分类号： G11C5/06 , H01L23/3121 , H01L24/48 , H01L24/73 , H01L24/94 , H01L24/97 , H01L25/03 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/05552 , H01L2224/0557 , H01L2224/06181 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73257 , H01L2224/81005 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/1052 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01055 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/00 , H01L2224/81 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.
摘要翻译：一些实施例包括具有多个存储器单元的设备和用于访问存储器单元的相关电路。器件的存储器单元可以形成在一个或多个存储器单元管芯中。设备的相关电路也可以形成在一个或多个骰子中，任选地与存储器单元骰子分开。

5. 发明授权

US08237254B2 Distributed semiconductor device methods, apparatus, and systems 有权
标题翻译：分布式半导体器件的方法，装置和系统
公开(公告)号：US08237254B2
公开(公告)日：2012-08-07
申请号：US13112863
申请日：2011-05-20
申请人： Paul A. Farrar , Hussein I Hanafi
发明人： Paul A. Farrar , Hussein I Hanafi
IPC分类号： H01L23/22 , H01L23/24
CPC分类号： G11C5/06 , H01L23/3121 , H01L24/48 , H01L24/73 , H01L24/94 , H01L24/97 , H01L25/03 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/05552 , H01L2224/0557 , H01L2224/06181 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73257 , H01L2224/81005 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/1052 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01055 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/00 , H01L2224/81 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.
摘要翻译：一些实施例包括具有多个存储器单元的设备和用于访问存储器单元的相关电路。器件的存储器单元可以形成在一个或多个存储器单元管芯中。设备的相关电路也可以形成在一个或多个骰子中，任选地与存储器单元骰子分开。

6. 发明授权

US07968960B2 Methods of forming strained semiconductor channels 有权
标题翻译：形成应变半导体通道的方法
公开(公告)号：US07968960B2
公开(公告)日：2011-06-28
申请号：US11506986
申请日：2006-08-18
申请人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
发明人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
IPC分类号： H01L21/76 , H01L21/425
CPC分类号： H01L29/7846 , H01L21/26506 , H01L21/7621 , H01L21/76232 , H01L29/0653 , H01L29/66568 , H01L29/7833 , H01L29/7842 , H01L29/7843 , H01L29/7849
摘要： In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein.
摘要翻译：在各种方法实施例中，限定半导体衬底中的器件区域和与器件区域相邻的隔离区域。器件区域具有沟道区域，并且隔离区域具有与沟道区域横向相邻的应变诱导区域。通道区域应变为用于载流子迁移率增强的期望应变，其中至少一种离子型注入能量，从而在隔离区域的应变诱导区域中产生峰值注入。本文提供了其它方面和实施例。

7. 发明授权

US07626252B2 Multi-chip electronic package and cooling system 失效
标题翻译：多芯片电子封装和冷却系统
公开(公告)号：US07626252B2
公开(公告)日：2009-12-01
申请号：US11300151
申请日：2005-12-13
申请人： Paul A. Farrar , Jerome M. Eldridge
发明人： Paul A. Farrar , Jerome M. Eldridge
IPC分类号： H01L23/02 , H01L23/34
CPC分类号： H01L23/42 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2225/06582 , H01L2225/06589
摘要： A multi-chip electronic package comprised of a plurality of integrated circuit chips secured together in a stack formation. The chip stack is hermetically sealed in an enclosure. The enclosure comprises a pressurized, thermally conductive fluid, which is utilized for cooling the enclosed chip stack. A process and structure is proposed that allows for densely-packed, multi-chip electronic packages to be manufactured with improved heat dissipation efficiency, thus improving the performance and reliability of the multi-chip electronic package.
摘要翻译：一种多芯片电子封装，由堆叠形成中固定在一起的多个集成电路芯片构成。芯片堆叠密封在外壳中。外壳包括加压的导热流体，其用于冷却封闭芯片堆叠。提出了一种可以制造具有提高的散热效率的密集封装的多芯片电子封装的工艺和结构，从而提高了多芯片电子封装的性能和可靠性。

8. 发明授权

US07592242B2 Apparatus and method for controlling diffusion 有权
标题翻译：用于控制扩散的装置和方法
公开(公告)号：US07592242B2
公开(公告)日：2009-09-22
申请号：US11215466
申请日：2005-08-30
申请人： Paul A. Farrar , Jerome M. Eldridge
发明人： Paul A. Farrar , Jerome M. Eldridge
IPC分类号： H01L21/33
CPC分类号： H01L29/207 , H01L21/26513 , H01L29/167
摘要： A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of dopant elements. Selection of a plurality of dopant elements includes selecting a first dopant element with a first atomic radius larger than a host matrix atomic radius and selecting a second dopant element with a second atomic radius smaller than a host matrix atomic radius. The methods and devices further include selecting amounts of each dopant element of the plurality of dopant elements wherein amounts and atomic radii of each of the plurality of dopant elements complement each other to reduce a host matrix lattice strain. The methods and devices further include introducing the plurality of dopant elements to a selected region of the host matrix and annealing the selected region of the host matrix.
摘要翻译：提供了用于降低掺杂半导体区域中的掺杂剂扩散速率的方法和装置。所述方法和装置包括选择多个掺杂元素。多个掺杂剂元素的选择包括选择具有大于主体矩阵原子半径的第一原子半径的第一掺杂元素，并且选择第二原子半径小于主矩阵原子半径的第二掺杂元素。所述方法和装置还包括选择多个掺杂元素中每个掺杂元素的量，其中多个掺杂元素中的每一个的量和原子半径相互补充以减少主矩阵晶格应变。所述方法和装置还包括将多个掺杂剂元素引入主体基质的选定区域并退火主体基质的选定区域。

9. 发明授权

US07560305B2 Apparatus and method for high density multi-chip structures 有权
标题翻译：高密度多芯片结构的装置和方法
公开(公告)号：US07560305B2
公开(公告)日：2009-07-14
申请号：US11218092
申请日：2005-08-31
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/5226 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2924/0002 , H01L2924/00
摘要： Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection structures and through chip connection structures. One advantage of this design includes an increased number of possible connections. Another advantage of this design includes shorter distances for interconnection pathways, which improves device performance and speed.
摘要翻译：描述了包括多芯片组件的装置和方法。提供了使用横向连接结构和芯片连接结构的多芯片组件的实施例。该设计的一个优点包括可能的连接数量的增加。这种设计的另一个优点包括互连路径的较短距离，这提高了设备性能和速度。

10. 发明申请

US20090108363A1 STRAINED SEMICONDUCTOR, DEVICES AND SYSTEMS AND METHODS OF FORMATION 有权
标题翻译：应变半导体，器件和系统及其形成方法
公开(公告)号：US20090108363A1
公开(公告)日：2009-04-30
申请号：US12346281
申请日：2008-12-30
申请人： Leonard Forbes , Paul A. Farrar
发明人： Leonard Forbes , Paul A. Farrar
IPC分类号： H01L27/088 , H01L29/06
CPC分类号： H01L29/7846 , H01L21/26506 , H01L21/76232 , H01L29/6659 , H01L29/7833
摘要： In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The device region has a channel region, and the isolation regions have volumes. The volumes of the isolation regions are adjusted to provide the channel region with a desired strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from a crystalline region to an amorphous region to expand the volumes of the isolation regions and provide the channel region with a desired compressive strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from an amorphous region to a crystalline region to contract the volumes of the isolation regions to provide the channel region with a desired tensile strain. Other aspects and embodiments are provided herein.
摘要翻译：在各种方法实施例中，器件区域被限定在半导体衬底中，并且隔离区域被限定为与器件区域相邻。器件区域具有通道区域，隔离区域具有体积。调整隔离区的体积以提供具有所需应变的通道区。在各种实施例中，调节隔离区域的体积包括将隔离区域从结晶区域转换为非晶区域以扩大隔离区域的体积并且为通道区域提供期望的压缩应变。在各种实施例中，调节隔离区域的体积包括将隔离区域从非晶区域转换为结晶区域以收缩隔离区域的体积，以提供具有期望拉伸应变的通道区域。本文提供了其它方面和实施例。

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