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1. 发明授权

US11048516B2 Systems, methods, and apparatuses for last branch record support compatible with binary translation and speculative execution using an architectural bit array and a write bit array 有权
公开(公告)号：US11048516B2
公开(公告)日：2021-06-29
申请号：US14752891
申请日：2015-06-27
申请人： Paul Caprioli , Koichi Yamada , Jason M. Agron , Jiwei Lu
发明人： Paul Caprioli , Koichi Yamada , Jason M. Agron , Jiwei Lu
IPC分类号： G06F9/38 , G06F9/30
摘要： Systems, methods, and apparatuses for last branch record support are described. In an embodiment, a hardware processor core comprises a hardware execution unit to execute a branch instruction, at least two last branch record (LBR) registers to store a source and destination information of a branch taken during program execution, wherein an entry in a LBR register is to include an encoding of the branch, a write bit array to indicate which LBR register is architecturally correct, an architectural bit array to indicate when an LBR register has been written, and a plurality of top of stack pointers to indicate which LBR register in a LBR register stack is to be written.

2. 发明授权

US09652234B2 Instruction and logic to control transfer in a partial binary translation system 有权
公开(公告)号：US09652234B2
公开(公告)日：2017-05-16
申请号：US13996352
申请日：2011-09-30
申请人： Paul Caprioli , Martin G. Dixon , Brett L. Toll , Muawya M. Al-Otoom , Omar M. Shaikh
发明人： Paul Caprioli , Martin G. Dixon , Brett L. Toll , Muawya M. Al-Otoom , Omar M. Shaikh
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/3808 , G06F9/3877 , G06F9/3887
摘要： A dynamic optimization of code for a processor-specific dynamic binary translation of hot code pages (e.g., frequently executed code pages) may be provided by a run-time translation layer. A method may be provided to use an instruction look-aside buffer (iTLB) to map original code pages and translated code pages. The method may comprise fetching an instruction from an original code page, determining whether the fetched instruction is a first instruction of a new code page and whether the original code page is deprecated. If both determinations return yes, the method may further comprise fetching a next instruction from a translated code page. If either determinations returns no, the method may further comprise decoding the instruction and fetching the next instruction from the original code page.

3. 发明申请

US20170097891A1 System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions 审中-公开
公开(公告)号：US20170097891A1
公开(公告)日：2017-04-06
申请号：US15382462
申请日：2016-12-16
申请人： Omar M. Shaikh , Ravi Rajwar , Paul Caprioli , Muawya M. Al-Otoom
发明人： Omar M. Shaikh , Ravi Rajwar , Paul Caprioli , Muawya M. Al-Otoom
IPC分类号： G06F12/0817 , G06F12/0842 , G06F9/38 , G06F11/14 , G06F9/46 , G06F9/30 , G06F12/084 , G06F12/0875
CPC分类号： G06F9/3855 , G06F9/3004 , G06F9/30043 , G06F9/3016 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F11/1448 , G06F11/1469 , G06F12/0828 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F2201/84 , G06F2212/1016 , G06F2212/452 , G06F2212/507 , G06F2212/6042 , G06F2212/62 , G06F2212/621 , G06F2213/0026
摘要： Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.

4. 发明授权

US09542191B2 Hardware profiling mechanism to enable page level automatic binary translation 有权
标题翻译：硬件分析机制，实现页面级自动二进制翻译
公开(公告)号：US09542191B2
公开(公告)日：2017-01-10
申请号：US13993792
申请日：2012-03-30
申请人： Paul Caprioli , Matthew C. Merten , Muawya M. Al-Otoom , Omar M. Shaikh , Abhay S. Kanhere , Suresh Srinivas , Koichi Yamada , Vivek Thakkar , Pawel Osciak
发明人： Paul Caprioli , Matthew C. Merten , Muawya M. Al-Otoom , Omar M. Shaikh , Abhay S. Kanhere , Suresh Srinivas , Koichi Yamada , Vivek Thakkar , Pawel Osciak
IPC分类号： G06F9/38 , G06F9/30 , G06F9/45 , G06F9/455
CPC分类号： G06F11/3466 , G06F8/40 , G06F8/52 , G06F9/3017 , G06F9/3842 , G06F9/4552 , G06F11/073 , G06F11/3616 , G06F11/3652
摘要： A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.
摘要翻译：通过性能监控硬件实现的硬件剖析机制可实现页面级自动二进制翻译。运行期间的硬件标识内存中包含潜在优化指令的代码页。硬件请求与代码页相关联的内存中的新页面的分配，其中新页面包含计数器的集合，并且每个计数器对应于代码页中的指令之一。当硬件检测到在代码页内具有分支目标的分支指令时，它增加与代码页中的分支目标相同的新页面中具有相同位置的计数器之一。代码页的执行被重复，并且当分支目标落在代码页内时计数器递增。然后硬件将新页面中的计数器值提供给用于二进制转换的二进制转换器。

5. 发明授权

US08732438B2 Anti-prefetch instruction 有权
标题翻译：反预取指令
公开(公告)号：US08732438B2
公开(公告)日：2014-05-20
申请号：US12104159
申请日：2008-04-16
申请人： Paul Caprioli , Sherman H. Yip , Gideon N. Levinsky
发明人： Paul Caprioli , Sherman H. Yip , Gideon N. Levinsky
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3867 , G06F12/0862
摘要： Embodiments of the present invention execute an anti-prefetch instruction. These embodiments start by decoding instructions in a decode unit in a processor to prepare the instructions for execution. Upon decoding an anti-prefetch instruction, these embodiments stall the decode unit to prevent decoding subsequent instructions. These embodiments then execute the anti-prefetch instruction, wherein executing the anti-prefetch instruction involves: (1) sending a prefetch request for a cache line in an L1 cache; (2) determining if the prefetch request hits in the L1 cache; (3) if the prefetch request hits in the L1 cache, determining if the cache line contains a predetermined value; and (4) conditionally performing subsequent operations based on whether the prefetch request hits in the L1 cache or the value of the data in the cache line.
摘要翻译：本发明的实施例执行反预取指令。这些实施例首先解码处理器中的解码单元中的指令，以准备执行指令。在对反预取指令进行解码时，这些实施例使解码单元停止以防止解码后续指令。这些实施例然后执行反预取指令，其中执行反预取指令涉及：（1）在L1高速缓存中发送用于高速缓存行的预取请求; （2）确定预取请求是否在L1高速缓存中命中; （3）如果预取请求命中在L1高速缓存中，则确定高速缓存线是否包含预定值; 以及（4）基于所述预提取请求是否在所述L1高速缓存中的命中或所述高速缓存行中的数据的值有条件地执行后续操作。

6. 发明申请

US20140095842A1 ACCELERATED INTERLANE VECTOR REDUCTION INSTRUCTIONS 有权
标题翻译：加速地面矢量减速指示
公开(公告)号：US20140095842A1
公开(公告)日：2014-04-03
申请号：US13630154
申请日：2012-09-28
申请人： Paul Caprioli , Abhay S. Kanhere , Jeffrey J. Cook , Muawya M. Al-Otoom
发明人： Paul Caprioli , Abhay S. Kanhere , Jeffrey J. Cook , Muawya M. Al-Otoom
IPC分类号： G06F9/302
CPC分类号： G06F9/30036 , G06F9/30014 , G06F9/30032 , G06F9/3012 , G06F9/3887 , G06F9/3893
摘要： A vector reduction instruction is executed by a processor to provide efficient reduction operations on an array of data elements. The processor includes vector registers. Each vector register is divided into a plurality of lanes, and each lane stores the same number of data elements. The processor also includes execution circuitry that receives the vector reduction instruction to reduce the array of data elements stored in a source operand into a result in a destination operand using a reduction operator. Each of the source operand and the destination operand is one of the vector registers. Responsive to the vector reduction instruction, the execution circuitry applies the reduction operator to two of the data elements in each lane, and shifts one or more remaining data elements when there is at least one of the data elements remaining in each lane.
摘要翻译：由处理器执行向量减少指令以对数据元素阵列提供有效的减少操作。处理器包括向量寄存器。每个向量寄存器被分成多个通道，每个通道存储相同数量的数据元素。处理器还包括执行电路，其接收向量减少指令，以使用缩减运算符将存储在源操作数中的数据元素的阵列减少到目标操作数的结果。源操作数和目标操作数中的每一个都是向量寄存器之一。响应于向量减少指令，执行电路将减法运算符应用于每个通道中的两个数据元素，并且当存在每个通道中的至少一个数据元素时，移位一个或多个剩余数据元素。

7. 发明申请

US20130305019A1 Instruction and Logic to Control Transfer in a Partial Binary Translation System 有权
标题翻译：控制部分二进制翻译系统传输的指令和逻辑
公开(公告)号：US20130305019A1
公开(公告)日：2013-11-14
申请号：US13996352
申请日：2011-09-30
申请人： Paul Caprioli , Martin G. Dixon , Brett L. Toll , Muawya M. Al-Otoom , Omar M. Shaikh
发明人： Paul Caprioli , Martin G. Dixon , Brett L. Toll , Muawya M. Al-Otoom , Omar M. Shaikh
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/3808 , G06F9/3877 , G06F9/3887
摘要： A dynamic optimization of code for a processor-specific dynamic binary translation of hot code pages (e.g., frequently executed code pages) may be provided by a run-time translation layer. A method may be provided to use an instruction look-aside buffer (iTLB) to map original code pages and translated code pages. The method may comprise fetching an instruction from an original code page, determining whether the fetched instruction is a first instruction of a new code page and whether the original code page is deprecated. If both determinations return yes, the method may further comprise fetching a next instruction from a translated code page. If either determinations returns no, the method may further comprise decoding the instruction and fetching the next instruction from the original code page.
摘要翻译：可以由运行时转换层提供用于热代码页（例如，经常执行的代码页）的处理器特定的动态二进制转换的代码的动态优化。可以提供一种方法来使用指令后备缓冲器（iTLB）来映射原始代码页和转换的代码页。该方法可以包括从原始代码页获取指令，确定所提取的指令是否是新代码页的第一指令以及原始代码页是否已被弃用。如果两个确定返回是，该方法还可以包括从转换的代码页获取下一个指令。如果任一确定返回否，则该方法还可以包括解码指令并从原始代码页获取下一条指令。

8. 发明申请

US20130283249A1 INSTRUCTION AND LOGIC TO PERFORM DYNAMIC BINARY TRANSLATION 有权
标题翻译：指令和逻辑执行动态二进制翻译
公开(公告)号：US20130283249A1
公开(公告)日：2013-10-24
申请号：US13995400
申请日：2011-09-30
申请人： Abhay S. Kanhere , Paul Caprioli , Koichi Yamada , Suriya Madras-Subramanian , Suresh Srinivas
发明人： Abhay S. Kanhere , Paul Caprioli , Koichi Yamada , Suriya Madras-Subramanian , Suresh Srinivas
IPC分类号： G06F9/45
CPC分类号： G06F8/40 , G06F8/456 , G06F8/51 , G06F9/30109 , G06F9/30185 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3877 , G06F9/3887 , G06F9/4552
摘要： A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic binary translation. The method may comprise executing original software code compiled targeting a first instruction set, using processor hardware to detect a hot spot in the software code and passing control to a binary translation translator, determining a hot spot region for translation, generating the translated code using a second instruction set, placing the translated code in a translation cache, executing the translated code from the translated cache, and transitioning back to the original software code after the translated code finishes execution.
摘要翻译：微架构可以提供硬件和软件协同设计的动态二进制翻译。微架构可以调用执行动态二进制转换的方法。该方法可以包括执行针对第一指令集编译的原始软件代码，使用处理器硬件来检测软件代码中的热点并将控制传递给二进制翻译翻译器，确定用于翻译的热点区域，使用第二指令集，将转换的代码放置在转换高速缓存中，从翻译的高速缓存中执行转换的代码，并且在转换的代码完成执行之后转换回原始软件代码。

9. 发明授权

US08484434B2 Index generation for cache memories 有权
标题翻译：高速缓存存储器的索引生成
公开(公告)号：US08484434B2
公开(公告)日：2013-07-09
申请号：US13402796
申请日：2012-02-22
申请人： Paul Caprioli , Martin Karlsson , Shailender Chaudhry
发明人： Paul Caprioli , Martin Karlsson , Shailender Chaudhry
IPC分类号： G06F13/12
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.
摘要翻译：本发明的实施例提供一种生成高速缓冲存储器的索引的系统。系统通过接收访问高速缓冲存储器的请求开始，其中请求包括地址信息。然后系统获得与请求相关联的非地址信息。接下来，系统使用地址信息和非地址信息来生成索引。然后，系统使用索引来实现对高速缓存的访问。

10. 发明授权

US08161273B2 Method and apparatus for programmatically rewinding a register inside a transaction 有权
标题翻译：用于在事务中以程序方式倒回寄存器的方法和装置
公开(公告)号：US08161273B2
公开(公告)日：2012-04-17
申请号：US12037636
申请日：2008-02-26
申请人： Paul Caprioli
发明人： Paul Caprioli
IPC分类号： G06F9/308 , G06F9/312
CPC分类号： G06F9/30123 , G06F9/3004 , G06F9/30087 , G06F9/3013 , G06F9/30145 , G06F9/3834 , G06F9/3863 , G06F9/462
摘要： Embodiments of the present invention provide a system that allocates registers in a processor. The system starts by commencing a transaction, wherein commencing the transaction involves preserving a pre-transactional state of registers in a first register file. The system then allocates one or more registers for temporary use during the transaction. Upon finishing using each allocated register during the transaction, the system executes an instruction that restores the allocated register to the pre-transactional state.
摘要翻译：本发明的实施例提供一种在处理器中分配寄存器的系统。系统从开始事务开始，其中开始事务涉及在第一寄存器文件中保留寄存器的事务前状态。然后系统在事务期间分配一个或多个临时使用的寄存器。一旦完成了在交易过程中使用每个分配的寄存器，系统将执行将所分配的寄存器恢复到事务前状态的指令。

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