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1. 发明授权

US08815700B2 Method of forming high lateral voltage isolation structure involving two separate trench fills 有权
标题翻译：形成高横向电压隔离结构的方法，涉及两个单独的沟槽填充
公开(公告)号：US08815700B2
公开(公告)日：2014-08-26
申请号：US12315934
申请日：2008-12-08
申请人： Peter J. Hopper , William French , Kyuwoon Hwang
发明人： Peter J. Hopper , William French , Kyuwoon Hwang
IPC分类号： H01L21/76
CPC分类号： H01L21/76283
摘要： In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench.
摘要翻译：在SOI工艺中，通过提供至少两个同心的电介质填充的沟槽来形成高横向电压隔离结构，去除介电填充的沟槽之间的半导体材料，并用电介质材料填充所得的间隙以限定单个宽的电介质填充的沟槽。

2. 发明授权

US08686722B2 Semiconductor fluxgate magnetometer 有权
标题翻译：半导体磁通门磁力计
公开(公告)号：US08686722B2
公开(公告)日：2014-04-01
申请号：US13218772
申请日：2011-08-26
申请人： Anuraag Mohan , Peter J. Hopper
发明人： Anuraag Mohan , Peter J. Hopper
IPC分类号： G01R33/04
CPC分类号： G01R33/04
摘要： A fluxgate magnetometer is formed in a semiconductor wafer fabrication sequence, which significantly reduces the size and cost of the fluxgate magnetometer. The semiconductor wafer fabrication sequence attaches a die, which has drive and sense circuits, to the bottom surface of a cavity formed in a larger structure, and forms drive and sense coils around a magnetic core structure on the top surface of the larger structure.
摘要翻译：磁通门磁力计形成在半导体晶片制造顺序中，这显着地减小了磁通门磁强计的尺寸和成本。半导体晶片制造顺序将具有驱动和感测电路的管芯附接到形成为较大结构的腔的底表面，并且在较大结构的顶表面上的磁芯结构周围形成驱动和感测线圈。

3. 发明授权

US08524548B2 DMOS Transistor with a cavity that lies below the drift region 有权
标题翻译：具有位于漂移区下方的空腔的DMOS晶体管
公开(公告)号：US08524548B2
公开(公告)日：2013-09-03
申请号：US13094645
申请日：2011-04-26
申请人： William French , Vladislav Vashchenko , Richard Wendell Foote, Jr. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
发明人： William French , Vladislav Vashchenko , Richard Wendell Foote, Jr. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
IPC分类号： H01L29/66
CPC分类号： H01L29/7824 , H01L21/26586 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66689 , H01L29/7835 , H01L29/78603
摘要： A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.
摘要翻译：形成在绝缘体上硅（SOI）结构上的横向DMOS晶体具有较高的击穿电压，该击穿电压是由在SOI结构的体区形成的空穴产生的。空腔暴露SOI结构的绝缘体层的底部表面的一部分，其直接位于DMOS晶体管的漂移区的垂直下方。

4. 发明授权

US08466535B2 Galvanic isolation fuse and method of forming the fuse 有权
标题翻译：电隔离保险丝和形成保险丝的方法
公开(公告)号：US08466535B2
公开(公告)日：2013-06-18
申请号：US13208890
申请日：2011-08-12
申请人： Peter J. Hopper , William French , Ann Gabrys , Martin Fallon
发明人： Peter J. Hopper , William French , Ann Gabrys , Martin Fallon
IPC分类号： H01L27/06
CPC分类号： H01L23/5256 , H01L23/48 , H01L25/0655 , H01L2224/48091 , H01L2224/48137 , H01L2224/48195 , H01L2924/10253 , H01L2924/13091 , H01L2924/30107 , H04L25/0266 , H01L2924/00015 , H01L2924/00 , H01L2924/00014
摘要： The spikes in current and voltage that result from the failure of a galvanic dielectric layer are safely contained by a galvanic isolation fuse that pops and forms and open circuit between a high-voltage die and a low-voltage die in response to the failure of the galvanic dielectric layer.
摘要翻译：由电流介电层故障引起的电流和电压尖峰由电流隔离保险丝安全地包含，该电隔离保险丝响应于高压管芯和低压管芯之间的电流隔离保险丝电介质层。

5. 发明申请

US20130049749A1 Semiconductor Fluxgate Magnetometer 有权
标题翻译：半导体磁通门磁力计
公开(公告)号：US20130049749A1
公开(公告)日：2013-02-28
申请号：US13218772
申请日：2011-08-26
申请人： Anuraag Mohan , Peter J. Hopper
发明人： Anuraag Mohan , Peter J. Hopper
IPC分类号： G01R33/02 , H01L43/12
CPC分类号： G01R33/04
摘要： A fluxgate magnetometer is formed in a semiconductor wafer fabrication sequence, which significantly reduces the size and cost of the fluxgate magnetometer. The semiconductor wafer fabrication sequence attaches a die, which has drive and sense circuits, to the bottom surface of a cavity formed in a larger structure, and forms drive and sense coils around a magnetic core structure on the top surface of the larger structure.
摘要翻译：磁通门磁力计形成在半导体晶片制造顺序中，这显着地减小了磁通门磁强计的尺寸和成本。半导体晶片制造顺序将具有驱动和感测电路的管芯附接到形成为较大结构的腔的底表面，并且在较大结构的顶表面上的磁芯结构周围形成驱动和感测线圈。

6. 发明申请

US20130001735A1 THERMALLY CONDUCTIVE SUBSTRATE FOR GALVANIC ISOLATION 有权
标题翻译：用于血液分离的导热基质
公开(公告)号：US20130001735A1
公开(公告)日：2013-01-03
申请号：US13170451
申请日：2011-06-28
申请人： Peter J. Hopper , William French , Ann Gabrys
发明人： Peter J. Hopper , William French , Ann Gabrys
IPC分类号： H01L29/02 , H01L21/50
CPC分类号： H01L23/3732 , H01L23/147 , H01L23/49894 , H01L25/0655 , H01L2224/16225 , H01L2224/48227 , H01L2924/10253 , H01L2924/19107 , H01L2924/00
摘要： A galvanic isolation integrated circuit system includes a semiconductor substrate; a layer of thermally conductive material, e.g., CVD nano- or poly-diamond thin film or boron nitride CVD thin film, formed over the semiconductor substrate; a first integrated circuit structure formed over the layer of thermally conductive material; a second integrated circuit structure formed over the layer of thermally conductive material, the second integrated circuit structure being spaced apart from the first integrated circuit structure; and a galvanic isolation structure formed over the layer of thermally conductive material between the first and second integrated circuit structures and connected to the first integrated circuit structure and the second integrated circuit structure.
摘要翻译：电隔离集成电路系统包括半导体衬底; 形成在半导体衬底上的导热材料层，例如CVD纳米或多晶金刚石薄膜或氮化硼CVD薄膜; 形成在导热材料层上的第一集成电路结构; 形成在所述导热材料层上的第二集成电路结构，所述第二集成电路结构与所述第一集成电路结构间隔开; 以及在第一和第二集成电路结构之间形成在导热材料层上并连接到第一集成电路结构和第二集成电路结构的电流隔离结构。

7. 发明授权

US08303484B2 Self-propelled robotic device that moves through bodily and other passageways 有权
标题翻译：通过身体和其他通道移动的自行式机器人装置
公开(公告)号：US08303484B2
公开(公告)日：2012-11-06
申请号：US12621719
申请日：2009-11-19
申请人： Peter J. Hopper , Philipp Lindorfer , William French , Visvamohan Yegnashankaran
发明人： Peter J. Hopper , Philipp Lindorfer , William French , Visvamohan Yegnashankaran
IPC分类号： A61B1/00
CPC分类号： A61B1/041 , A61B1/00082 , A61B1/00156 , A61B1/005 , A61B1/31 , A61B8/12 , A61B8/429 , A61B8/4472
摘要： A self-propelled robotic device moves through bodily and other passageways by inflating regions of an overlying bladder along the length of the robotic device in a sequence that imparts motion to the device. The regions of the overlying bladder are inflated by energizing a plurality of coils, which are surrounded by a ferrofluid, in a sequence. The ferrofluid responds to the magnetic field created by an energized coil by creating a bulge in the side wall of the overlying bladder.
摘要翻译：自动推进的机器人装置通过身体和其他通道沿着机器人装置的长度沿着向装置施加运动的顺序使覆盖的膀胱的区域膨胀而移动。通过对由铁磁流体包围的多个线圈进行顺序地激励上覆的气囊的区域来充气。铁磁流体通过在上覆气囊的侧壁中产生凸起来响应由通电线圈产生的磁场。

8. 发明授权

US08098121B2 Method of switching a magnetic MEMS switch 有权
标题翻译：切换磁性MEMS开关的方法
公开(公告)号：US08098121B2
公开(公告)日：2012-01-17
申请号：US12852743
申请日：2010-08-09
申请人： Peter J Hopper , Trevor Niblock , Peter Johnson , Vladislav Vashchenko
发明人： Peter J Hopper , Trevor Niblock , Peter Johnson , Vladislav Vashchenko
IPC分类号： H01H51/22 , H01H51/34
CPC分类号： H02M3/34
摘要： A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impulses applied by an associated motion oscillator, which can be magnetic or electric actuators.
摘要翻译： MEMS磁通开关被制造为铁磁芯。芯包括中心悬臂，其被制造为可以以其机械和材料性质确定的共振频率振荡的自由梁。中心悬臂由相关运动振荡器施加的脉冲移动，运动振荡器可以是磁性或电动执行器。

9. 发明申请

US20110272780A1 METHOD AND STRUCTURE FOR IMPROVING THE QUALILTY FACTOR OF RF INDUCTORS 审中-公开
标题翻译：改进射频电感器质量因子的方法和结构
公开(公告)号：US20110272780A1
公开(公告)日：2011-11-10
申请号：US12774532
申请日：2010-05-05
申请人： Peter Smeys , Kyuwoon Hwang , Peter J. Hopper , William French
发明人： Peter Smeys , Kyuwoon Hwang , Peter J. Hopper , William French
IPC分类号： H01L29/86 , H01L21/02
CPC分类号： H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： An on-chip inductor structure is formed as part of an integrated circuit structure. The integrate circuit structure includes a semiconductor substrate having a top side and a back side, integrated circuit elements formed on the top side of the substrate, a conductive interconnect structure formed in contact with the integrated circuit elements and a passivation layer formed over the integrated circuit elements. The inductor structure comprises a layer of photoimageable epoxy formed on the passivation layer, a conductive inductor coil formed on the layer of photoimageable epoxy and at least one conductive via that extends from the inductor coil to the interconnect layer to provide electrical connection therebetween. Additionally, a back side trench may be formed in the back side of the semiconductor substrate beneath the inductor coil.
摘要翻译：片上电感器结构形成为集成电路结构的一部分。集成电路结构包括具有顶侧和背面的半导体衬底，形成在衬底的顶侧上的集成电路元件，与集成电路元件接触形成的导电互连结构和形成在集成电路上的钝化层元素。电感器结构包括形成在钝化层上的可光成像环氧树脂层，形成在可光成像环氧树脂层上的导电电感线圈和从电感线圈延伸到互连层的至少一个导电通孔，以在它们之间提供电连接。此外，可以在电感线圈下方的半导体衬底的背面形成背面沟槽。

10. 发明授权

US07978519B2 Method of reading an NVM cell that utilizes a gated diode 有权
标题翻译：读取利用门控二极管的NVM单元的方法
公开(公告)号：US07978519B2
公开(公告)日：2011-07-12
申请号：US12884567
申请日：2010-09-17
申请人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
发明人： Yuri Mirgorodski , Peter J. Hopper , Roozbeh Parsa
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A method of reading an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain region defining an n-type cannel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and drain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and is separated therefrom by intervening dielectric material, the method comprising: biasing the deep N-type well at a preselected read voltage; holding the source region of the PMOS transistor at the read voltage; holding the drain of the PMOS transistor at ground; and holding the control gate at ground for a preselected read time.
摘要翻译：一种读取在N型半导体材料的深阱中形成的NVM单元结构的方法，其中所述NVM单元结构包括形成在N型阱中的PMOS晶体管，所述PMOS晶体管包括间隔开的p型源极和漏极区域，其间形成n型沟道区域，形成在与N型阱相邻的P型阱中的NMOS晶体管，所述NMOS晶体管包括间隔开的n型源极和漏极区，其限定p型沟道导电浮置栅极，其包括在PMOS晶体管的n型沟道区域上延伸并且通过中间介电材料分离的第一部分和在p型沟道区域上延伸并与其分离的第二部分的第一部分通过插入电介质材料和导电控制栅极形成在浮动栅极的第二部分的至少一部分上，并通过介电材料与其分离，该方法com 奖励：以预选的读取电压偏置深N型阱; 将PMOS晶体管的源极区域保持在读取电压; 将PMOS晶体管的漏极保持在地; 并将控制门保持在地面以进行预选的读取时间。

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