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1. 发明授权

US09709303B1 Magneto-caloric cooling system 有权
公开(公告)号：US09709303B1
公开(公告)日：2017-07-18
申请号：US13308378
申请日：2011-11-30
申请人： Nader G. Dariavach , Jin Liang , F. William French , Boris I. Shusterman
发明人： Nader G. Dariavach , Jin Liang , F. William French , Boris I. Shusterman
IPC分类号： F25B21/00
CPC分类号： F25B21/00 , F25B2321/002 , Y02B30/66
摘要： A magneto-caloric cooling system includes an energy absorption area configured to be thermally coupled to a thermal energy absorbing device. At least one energy dissipation area is configured to be thermally coupled to a thermal energy dissipation device. A thermal energy transfer device is configured to be cycled between the energy absorption area and the energy dissipation area. A magnetic field generation device is configured to produce a magnetic field proximate the energy dissipation area.

2. 发明授权

US08815700B2 Method of forming high lateral voltage isolation structure involving two separate trench fills 有权
标题翻译：形成高横向电压隔离结构的方法，涉及两个单独的沟槽填充
公开(公告)号：US08815700B2
公开(公告)日：2014-08-26
申请号：US12315934
申请日：2008-12-08
申请人： Peter J. Hopper , William French , Kyuwoon Hwang
发明人： Peter J. Hopper , William French , Kyuwoon Hwang
IPC分类号： H01L21/76
CPC分类号： H01L21/76283
摘要： In a SOI process, a high lateral voltage isolation structure is formed by providing at least two concentric dielectric filled trenches, removing the semiconductor material between the dielectric filled trenches and filling the resultant gap with dielectric material to define a single wide dielectric filled trench.
摘要翻译：在SOI工艺中，通过提供至少两个同心的电介质填充的沟槽来形成高横向电压隔离结构，去除介电填充的沟槽之间的半导体材料，并用电介质材料填充所得的间隙以限定单个宽的电介质填充的沟槽。

3. 发明授权

US08585587B2 Determining phase variation of light in an endoscope 有权
标题翻译：确定内窥镜中的光的相位变化
公开(公告)号：US08585587B2
公开(公告)日：2013-11-19
申请号：US13003387
申请日：2009-07-09
申请人： Paul Michael William French , Carl Paterson , Mark Andrew Aquilla Neil , Christopher William Dunsby
发明人： Paul Michael William French , Carl Paterson , Mark Andrew Aquilla Neil , Christopher William Dunsby
IPC分类号： A61B1/07
CPC分类号： G02B23/2453 , A61B1/00165 , A61B1/00172 , A61B1/043 , A61B5/0068 , A61B5/0071 , A61B5/0084 , G02B23/26
摘要： An endoscope includes a light source operable to generate coherent incident light, and a plurality of imaging optical fibers that are arranged in a fiber bundle, arranged to receive light at a proximal end of the fiber bundle, and arranged to transmit light to a distal end of the fiber bundle. The endoscope further includes a spatial light phase modulator between the light source and the fiber bundle, and arranged to receive the incident light from the light source and to adjust the relative phase of the incident light entering each of the plurality of imaging optical fibers.
摘要翻译：内窥镜包括可操作以产生相干入射光的光源和布置成纤维束中的多个成像光纤，其布置成在光纤束的近端处接收光，并且布置成将光透射到远端的纤维束。内窥镜还包括在光源和光纤束之间的空间光相位调制器，并被布置成接收来自光源的入射光并调节入射到多个成像光纤中的每一个的入射光的相对相位。

4. 发明授权

US08524548B2 DMOS Transistor with a cavity that lies below the drift region 有权
标题翻译：具有位于漂移区下方的空腔的DMOS晶体管
公开(公告)号：US08524548B2
公开(公告)日：2013-09-03
申请号：US13094645
申请日：2011-04-26
申请人： William French , Vladislav Vashchenko , Richard Wendell Foote, Jr. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
发明人： William French , Vladislav Vashchenko , Richard Wendell Foote, Jr. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
IPC分类号： H01L29/66
CPC分类号： H01L29/7824 , H01L21/26586 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66689 , H01L29/7835 , H01L29/78603
摘要： A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.
摘要翻译：形成在绝缘体上硅（SOI）结构上的横向DMOS晶体具有较高的击穿电压，该击穿电压是由在SOI结构的体区形成的空穴产生的。空腔暴露SOI结构的绝缘体层的底部表面的一部分，其直接位于DMOS晶体管的漂移区的垂直下方。

5. 发明授权

US08466535B2 Galvanic isolation fuse and method of forming the fuse 有权
标题翻译：电隔离保险丝和形成保险丝的方法
公开(公告)号：US08466535B2
公开(公告)日：2013-06-18
申请号：US13208890
申请日：2011-08-12
申请人： Peter J. Hopper , William French , Ann Gabrys , Martin Fallon
发明人： Peter J. Hopper , William French , Ann Gabrys , Martin Fallon
IPC分类号： H01L27/06
CPC分类号： H01L23/5256 , H01L23/48 , H01L25/0655 , H01L2224/48091 , H01L2224/48137 , H01L2224/48195 , H01L2924/10253 , H01L2924/13091 , H01L2924/30107 , H04L25/0266 , H01L2924/00015 , H01L2924/00 , H01L2924/00014
摘要： The spikes in current and voltage that result from the failure of a galvanic dielectric layer are safely contained by a galvanic isolation fuse that pops and forms and open circuit between a high-voltage die and a low-voltage die in response to the failure of the galvanic dielectric layer.
摘要翻译：由电流介电层故障引起的电流和电压尖峰由电流隔离保险丝安全地包含，该电隔离保险丝响应于高压管芯和低压管芯之间的电流隔离保险丝电介质层。

6. 发明申请

US20130001735A1 THERMALLY CONDUCTIVE SUBSTRATE FOR GALVANIC ISOLATION 有权
标题翻译：用于血液分离的导热基质
公开(公告)号：US20130001735A1
公开(公告)日：2013-01-03
申请号：US13170451
申请日：2011-06-28
申请人： Peter J. Hopper , William French , Ann Gabrys
发明人： Peter J. Hopper , William French , Ann Gabrys
IPC分类号： H01L29/02 , H01L21/50
CPC分类号： H01L23/3732 , H01L23/147 , H01L23/49894 , H01L25/0655 , H01L2224/16225 , H01L2224/48227 , H01L2924/10253 , H01L2924/19107 , H01L2924/00
摘要： A galvanic isolation integrated circuit system includes a semiconductor substrate; a layer of thermally conductive material, e.g., CVD nano- or poly-diamond thin film or boron nitride CVD thin film, formed over the semiconductor substrate; a first integrated circuit structure formed over the layer of thermally conductive material; a second integrated circuit structure formed over the layer of thermally conductive material, the second integrated circuit structure being spaced apart from the first integrated circuit structure; and a galvanic isolation structure formed over the layer of thermally conductive material between the first and second integrated circuit structures and connected to the first integrated circuit structure and the second integrated circuit structure.
摘要翻译：电隔离集成电路系统包括半导体衬底; 形成在半导体衬底上的导热材料层，例如CVD纳米或多晶金刚石薄膜或氮化硼CVD薄膜; 形成在导热材料层上的第一集成电路结构; 形成在所述导热材料层上的第二集成电路结构，所述第二集成电路结构与所述第一集成电路结构间隔开; 以及在第一和第二集成电路结构之间形成在导热材料层上并连接到第一集成电路结构和第二集成电路结构的电流隔离结构。

7. 发明授权

US08303484B2 Self-propelled robotic device that moves through bodily and other passageways 有权
标题翻译：通过身体和其他通道移动的自行式机器人装置
公开(公告)号：US08303484B2
公开(公告)日：2012-11-06
申请号：US12621719
申请日：2009-11-19
申请人： Peter J. Hopper , Philipp Lindorfer , William French , Visvamohan Yegnashankaran
发明人： Peter J. Hopper , Philipp Lindorfer , William French , Visvamohan Yegnashankaran
IPC分类号： A61B1/00
CPC分类号： A61B1/041 , A61B1/00082 , A61B1/00156 , A61B1/005 , A61B1/31 , A61B8/12 , A61B8/429 , A61B8/4472
摘要： A self-propelled robotic device moves through bodily and other passageways by inflating regions of an overlying bladder along the length of the robotic device in a sequence that imparts motion to the device. The regions of the overlying bladder are inflated by energizing a plurality of coils, which are surrounded by a ferrofluid, in a sequence. The ferrofluid responds to the magnetic field created by an energized coil by creating a bulge in the side wall of the overlying bladder.
摘要翻译：自动推进的机器人装置通过身体和其他通道沿着机器人装置的长度沿着向装置施加运动的顺序使覆盖的膀胱的区域膨胀而移动。通过对由铁磁流体包围的多个线圈进行顺序地激励上覆的气囊的区域来充气。铁磁流体通过在上覆气囊的侧壁中产生凸起来响应由通电线圈产生的磁场。

8. 发明申请

US20110272780A1 METHOD AND STRUCTURE FOR IMPROVING THE QUALILTY FACTOR OF RF INDUCTORS 审中-公开
标题翻译：改进射频电感器质量因子的方法和结构
公开(公告)号：US20110272780A1
公开(公告)日：2011-11-10
申请号：US12774532
申请日：2010-05-05
申请人： Peter Smeys , Kyuwoon Hwang , Peter J. Hopper , William French
发明人： Peter Smeys , Kyuwoon Hwang , Peter J. Hopper , William French
IPC分类号： H01L29/86 , H01L21/02
CPC分类号： H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： An on-chip inductor structure is formed as part of an integrated circuit structure. The integrate circuit structure includes a semiconductor substrate having a top side and a back side, integrated circuit elements formed on the top side of the substrate, a conductive interconnect structure formed in contact with the integrated circuit elements and a passivation layer formed over the integrated circuit elements. The inductor structure comprises a layer of photoimageable epoxy formed on the passivation layer, a conductive inductor coil formed on the layer of photoimageable epoxy and at least one conductive via that extends from the inductor coil to the interconnect layer to provide electrical connection therebetween. Additionally, a back side trench may be formed in the back side of the semiconductor substrate beneath the inductor coil.
摘要翻译：片上电感器结构形成为集成电路结构的一部分。集成电路结构包括具有顶侧和背面的半导体衬底，形成在衬底的顶侧上的集成电路元件，与集成电路元件接触形成的导电互连结构和形成在集成电路上的钝化层元素。电感器结构包括形成在钝化层上的可光成像环氧树脂层，形成在可光成像环氧树脂层上的导电电感线圈和从电感线圈延伸到互连层的至少一个导电通孔，以在它们之间提供电连接。此外，可以在电感线圈下方的半导体衬底的背面形成背面沟槽。

9. 发明申请

US20110233670A1 METHOD OF FORMING A REGION OF GRADED DOPING CONCENTRATION IN A SEMICONDUCTOR DEVICE AND RELATED APPARATUS 有权
标题翻译：形成半导体器件中的分级掺杂浓度区域的方法及相关装置
公开(公告)号：US20110233670A1
公开(公告)日：2011-09-29
申请号：US13156184
申请日：2011-06-08
申请人： William French , Erika Mazotti , Yuri Mirgorodski
发明人： William French , Erika Mazotti , Yuri Mirgorodski
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/2253 , H01L29/0653 , H01L29/1045 , H01L29/66659 , H01L29/7835
摘要： A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile.
摘要翻译：用于形成半导体器件的掺杂区域的方法包括用掩模掩蔽衬底的一部分。掩模被配置为在掺杂区域内产生渐变掺杂分布。该方法还包括使用掩模执行植入物以在衬底中产生掺杂区域和未掺杂区域。该方法还包括扩散掺杂区域以在掺杂区域中产生渐变掺杂分布。掩模可以包括具有分布在整个光致抗蚀剂材料中的开口的第一区域，其中开口的尺寸和间隔变化。掩模还可以包括具有分布在整个开放区域中的光致抗蚀剂材料块的第二区域，其中光刻胶块的尺寸和间距变化。扩散掺杂区域可以包括施加高温退火以使掺杂和未掺杂区域平滑以产生线性渐变的掺杂分布。

10. 发明授权

US07968913B2 CMOS compatable fabrication of power GaN transistors on a <100> silicon substrate 有权
标题翻译：在<100>硅衬底上的CMOS兼容制造功率GaN晶体管
公开(公告)号：US07968913B2
公开(公告)日：2011-06-28
申请号：US12315931
申请日：2008-12-08
申请人： Peter J. Hopper , William French
发明人： Peter J. Hopper , William French
IPC分类号： H01L29/778
CPC分类号： H01L29/045 , H01L21/8258 , H01L29/0843 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/7786
摘要： In an AlGaN channel transistor formed on a orientation silicon wafer, a hole with walls slanted at 54 degrees is etched into the silicon to provide a orientation substrate surface for forming the AlGaN channel transistor.
摘要翻译：在形成在<100>取向硅晶片上的AlGaN沟道晶体管中，将以54度倾斜的壁的孔蚀刻到硅中，以提供用于形成AlGaN沟道晶体管的<111>取向衬底表面。

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