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1. 发明授权

US07426672B2 Method for implementing processor bus speculative data completion 失效
标题翻译：实现处理器总线推测数据完成的方法
公开(公告)号：US07426672B2
公开(公告)日：2008-09-16
申请号：US11116624
申请日：2005-04-28
申请人： Wayne Melvin Barrett , Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
发明人： Wayne Melvin Barrett , Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
IPC分类号： H03M13/00
CPC分类号： G06F11/10
摘要： A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.
摘要翻译：提供了一种用于在计算机系统中实现处理器总线推测数据完成的方法和装置。计算机系统中的存储器控制器将未校正的数据从存储器发送到处理器总线。存储器控制器还将未校正的数据应用于纠错码（ECC）校验和校正电路。当检测到单个位错误（SBE）时，校正的数据在未校正的数据之后被发送到处理器总线预定数量的周期。

2. 发明授权

US07328315B2 System and method for managing mirrored memory transactions and error recovery 有权
标题翻译：用于管理镜像内存事务和错误恢复的系统和方法
公开(公告)号：US07328315B2
公开(公告)日：2008-02-05
申请号：US11050291
申请日：2005-02-03
申请人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
发明人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
IPC分类号： G06F12/00
CPC分类号： G06F11/1666 , G06F11/141 , G06F11/20
摘要： In a data processing system having a memory control device including at least two mirrored memory ports, a method, system, and article of manufacture for processing read requests are disclosed herein. In accordance with the method of the present invention, a read request is received on a system interconnect coupling read requestors with memory resources. The received read request is issued only to a specified one of the at least two mirrored memory ports within the memory control device. In response to detecting an unrecoverable error resulting from the read request issued to the one mirrored memory port, the received read request is issued to an alternate of the at least two mirrored memory ports.
摘要翻译：在具有包括至少两个镜像存储器端口的存储器控制装置的数据处理系统中，本文公开了一种用于处理读请求的方法，系统和制品。根据本发明的方法，在将读请求者与存储器资源耦合的系统互连上接收到读请求。所接收的读取请求仅发送到存储器控制设备内的至少两个镜像存储器端口中的指定的一个。响应于检测到从所发送到所述一个镜像存储器端口的读取请求而导致的不可恢复的错误，所接收的读取请求被发布到所述至少两个镜像存储器端口的替代。

3. 发明授权

US07013375B2 Configurable directory allocation 有权
标题翻译：可配置的目录分配
公开(公告)号：US07013375B2
公开(公告)日：2006-03-14
申请号：US10403157
申请日：2003-03-31
申请人： John Michael Borkenhagen , Philip Rogers Hillier, III , Russell Dean Hoover
发明人： John Michael Borkenhagen , Philip Rogers Hillier, III , Russell Dean Hoover
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： Methods, apparatus, and program product are disclosed for use in a computer system in which one or more multiprocessor nodes comprise the computer system. The methods and apparatus provide for configurable allocation of a memory in a node memory controller. In a single node implementation of the computer system, substantially all of the memory is allocated to a snoop directory used to store directory entries for cache lines used by processors in the node. In computer system implementations having more than one node, the amount of the memory allocated to the snoop directory and the amount of the memory allocated to a remote memory directory is controlled respondent to predetermined sizes respondent to the number of nodes in the computer system.
摘要翻译：公开了用于其中一个或多个多处理器节点包括计算机系统的计算机系统中的方法，装置和程序产品。所述方法和装置提供节点存储器控制器中的存储器的可配置分配。在计算机系统的单个节点实现中，基本上所有的存储器被分配给用于存储节点中的处理器使用的高速缓存行的目录条目的窥探目录。在具有多于一个节点的计算机系统实现中，分配给窥探目录的存储器的量和分配给远程存储器目录的存储器的量被控制为响应于计算机系统中的节点数量的预定大小。

4. 发明授权

US08082396B2 Selecting a command to send to memory 失效
标题翻译：选择要发送到内存的命令
公开(公告)号：US08082396B2
公开(公告)日：2011-12-20
申请号：US11116626
申请日：2005-04-28
申请人： Herman Lee Blackmon , Philip Rogers Hillier, III , Joseph Allen Kirscht , Brian T. Vanderpool
发明人： Herman Lee Blackmon , Philip Rogers Hillier, III , Joseph Allen Kirscht , Brian T. Vanderpool
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F13/1642
摘要： A method, apparatus, system, and signal-bearing medium that, in an embodiment, select a command to send to memory. In an embodiment, the oldest command in a write queue that does not collide with a conflict queue is sent to memory and added to the conflict queue if some or all of the following are true: all of the commands in the read queue collide with the conflict queue, any read command incoming from the processor does not collide with the write queue, the number of commands in the write queue is greater than a first threshold, and all commands in the conflict queue have been present for less than a second threshold. In an embodiment, a command does not collide with a queue if the command does not access the same cache line in memory as the commands in the queue. In this way, in an embodiment, write commands are sent to the memory at a time that reduces the impact on the performance of read commands.
摘要翻译：在一个实施例中，选择要发送到存储器的命令的方法，装置，系统和信号承载介质。在一个实施例中，写入队列中与冲突队列不冲突的最早的命令被发送到存储器，并且如果以下部分或全部为真，则将其添加到冲突队列中：读队列中的所有命令与冲突队列，从处理器传入的任何读取命令都不会与写入队列冲突，写入队列中的命令数量大于第一个阈值，并且冲突队列中的所有命令都存在少于第二个阈值。在一个实施例中，如果命令不访问存储器中与队列中的命令相同的高速缓存行，则命令不与队列冲突。以这种方式，在一个实施例中，写入命令在减少对读取命令的性能的影响的时刻被发送到存储器。

5. 发明授权

US07908443B2 Memory controller and method for optimized read/modify/write performance 失效
标题翻译：用于优化读/写/写性能的内存控制器和方法
公开(公告)号：US07908443B2
公开(公告)日：2011-03-15
申请号：US12136750
申请日：2008-06-10
申请人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
发明人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.
摘要翻译：存储器控制器通过将RMW命令分解成不需要一起执行的单独且唯一的读取和写入命令来优化执行读/修改/写入命令，但只需要以正确的顺序执行。最优选的实施例结合读队列和写队列使用控制器中的单独的RMW队列。在其他实施例中，控制器将RMW的读取和写入部分放置在读取和写入队列中，但是写入队列具有与写入队列中的RMW写入命令相关联的依赖指示，以确保控制器维持正确的执行顺序。实施例允许存储器控制器以正确的执行顺序将RMW命令转换为读写命令以保持数据一致性。

6. 发明授权

US07475202B2 Memory controller and method for optimized read/modify/write performance 有权
标题翻译：用于优化读/写/写性能的内存控制器和方法
公开(公告)号：US07475202B2
公开(公告)日：2009-01-06
申请号：US11779277
申请日：2007-07-18
申请人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
发明人： Philip Rogers Hillier, III , William Paul Hovis , Joseph Allen Kirscht
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.
摘要翻译：存储器控制器通过将RMW命令分解成不需要一起执行的单独且唯一的读取和写入命令来优化执行读/修改/写入命令，但只需要以正确的顺序执行。最优选的实施例结合读队列和写队列使用控制器中的单独的RMW队列。在其他实施例中，控制器将RMW的读取和写入部分放置在读取和写入队列中，但是写入队列具有与写入队列中的RMW写入命令相关联的依赖指示，以确保控制器维持正确的执行顺序。实施例允许存储器控制器以正确的执行顺序将RMW命令转换为读写命令以保持数据一致性。

7. 发明授权

US07472236B2 Managing mirrored memory transactions and error recovery 失效
标题翻译：管理镜像内存事务和错误恢复
公开(公告)号：US07472236B2
公开(公告)日：2008-12-30
申请号：US11927901
申请日：2007-10-30
申请人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
发明人： Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
IPC分类号： G06F12/00
CPC分类号： G06F11/1666 , G06F11/141 , G06F11/20
摘要： In a data processing system having a memory control device including at least two mirrored memory ports, a method and computer-readable medium for processing read requests are disclosed herein. In accordance with the method of the present invention, a read request is received on a system interconnect coupling read requestors with memory resources. The received read request is issued only to a specified one of the at least two mirrored memory ports within the memory control device. In response to detecting an unrecoverable error resulting from the read request issued to the one mirrored memory port, the received read request is issued to an alternate of the at least two mirrored memory ports.
摘要翻译：在具有包括至少两个镜像存储器端口的存储器控制装置的数据处理系统中，本文公开了一种用于处理读取请求的方法和计算机可读介质。根据本发明的方法，在将读请求者与存储器资源耦合的系统互连上接收到读请求。所接收的读取请求仅发送到存储器控制设备内的至少两个镜像存储器端口中的指定的一个。响应于检测到从所发送到所述一个镜像存储器端口的读取请求而导致的不可恢复的错误，所接收的读取请求被发布到所述至少两个镜像存储器端口的替代。

8. 发明授权

US07467260B2 Method and apparatus to purge remote node cache lines to support hot node replace in a computing system 有权
标题翻译：清除远程节点缓存行以支持计算系统中的热节点替换的方法和装置
公开(公告)号：US07467260B2
公开(公告)日：2008-12-16
申请号：US10961746
申请日：2004-10-08
申请人： Duane Arlyn Averill , John Michael Borkenhagen , Philip Rogers Hillier, III
发明人： Duane Arlyn Averill , John Michael Borkenhagen , Philip Rogers Hillier, III
IPC分类号： G06F12/00
CPC分类号： G06F12/0808 , G06F12/0804 , G06F12/126
摘要： An apparatus and method is disclosed for flushing a cache in a computing system. In a multinode computing system a cache in a first node may contain modified data in an address space of a second node. The cache in the first node must be purged prior to shutting down the first node. The computing system uses a random class replacement scheme for the cache. A cache flush routine sets a cache flush mode in a class replace select mechanism, overriding the random class replacement scheme. With the random class replacement scheme overridden, a minimum number of fetches will flush all the cache lines in the cache, each fetch loading the cache with a cache line not already in the cache. No additional delay penalty is incurred in a critical path through which fetches and stores to the cache must pass.
摘要翻译：公开了一种用于在计算系统中刷新高速缓存的装置和方法。在多节点计算系统中，第一节点中的高速缓存可以包含第二节点的地址空间中的修改数据。必须在关闭第一个节点之前清除第一个节点中的缓存。计算系统对缓存使用随机类替换方案。缓存刷新例程在类替换选择机制中设置缓存刷新模式，覆盖随机类替换方案。随着随机类替换方案被覆盖，最小数量的提取将刷新缓存中的所有高速缓存行，每次使用尚未在高速缓存中的缓存行来提取缓存。在缓存提取和存储必须通过的关键路径中不会产生额外的延迟损失。

9. 发明授权

US5907702A Method and apparatus for decreasing thread switch latency in a multithread processor 失效
标题翻译：减少多线程处理器中线程切换延迟的方法和装置
公开(公告)号：US5907702A
公开(公告)日：1999-05-25
申请号：US829518
申请日：1997-03-28
申请人： William Thomas Flynn , Philip Rogers Hillier, III
发明人： William Thomas Flynn , Philip Rogers Hillier, III
IPC分类号： G06F9/38 , G06F9/46 , G06F9/00
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3851 , G06F9/461
摘要： The method and apparatus for decreasing thread switch latency in a multithread processor stores instructions for an active thread in a primary instruction queue, and stores instructions for a dormant thread in a thread switch instruction queue. The active thread is the thread currently being processed by the multithread processor, while the dormant thread is a thread not currently being executed by the multithread processor. During execution of the active thread, instructions are dispatched from the primary instruction queue for processing. When a thread switch occurs, instructions are dispatched from the thread switch instruction queue for execution. Simultaneously, instructions stored in the thread switch instruction queue are transferred to the primary instruction queue. In this manner, the thread switch latency resulting from the amount of time to refill the primary instruction queue with instructions of the dormant thread is eliminated.
摘要翻译：用于减少多线程处理器中的线程切换等待时间的方法和装置存储主要指令队列中的活动线程的指令，并将休眠线程的指令存储在线程切换指令队列中。活动线程是当前正在由多线程处理器处理的线程，而休眠线程是当前由多线程处理器执行的线程。在执行活动线程期间，从主指令队列调度指令进行处理。当发生线程切换时，将从线程切换指令队列中分派指令进行执行。同时，存储在线程切换指令队列中的指令被传送到主指令队列。以这种方式，消除了由休眠线程的指令重新填充主指令队列的时间量所导致的线程切换延迟。

10. 发明申请

US20110261821A1 IMPLEMENTING GHOST PACKET REMOVAL WITHIN A RELIABLE MESHED NETWORK 失效
标题翻译：在可靠的网络中实现GHOST包的拆卸
公开(公告)号：US20110261821A1
公开(公告)日：2011-10-27
申请号：US12764193
申请日：2010-04-21
申请人： Philip Rogers Hillier, III , David Alan Shedivy , Kenneth Michael Valk , Bruce Marshall Walk
发明人： Philip Rogers Hillier, III , David Alan Shedivy , Kenneth Michael Valk , Bruce Marshall Walk
IPC分类号： H04L12/56
CPC分类号： H04L47/34 , H04L45/245 , H04L49/552
摘要： A method and circuit for implementing multiple active paths between source and destination devices in an interconnect system while removing ghost packets, and a design structure on which the subject circuit resides are provided. Each packet includes a generation ID and is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The packets are transmitted from a source interconnect chip source to a destination interconnect chip on the multiple active paths. The generation ID of a received packet is compared with a current generation ID at a destination interconnect chip to validate packet acceptance. The destination interconnect chip uses the ETE sequence numbers to reorder the accepted received packets into the correct order before sending the packets to the destination device.
摘要翻译：一种用于在去除重影分组的同时在互连系统中的源和目的设备之间实现多个活动路径的方法和电路，以及提供了所述主题电路所在的设计结构。每个分组包括生成ID，并且在源互连芯片中分配表示来自源设备的有序分组流中的分组位置的端到端（ETE）序列号。分组从源互连芯片源传输到多个主动路径上的目的地互连芯片。将接收到的分组的生成ID与目的地互连芯片上的当前生成ID进行比较，以验证分组接受。目的互连芯片在将数据包发送到目标设备之前，使用ETE序列号将接收的接收数据包重新排序为正确的顺序。

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