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1. 发明授权

US08685877B2 Doping of nanostructures 有权
标题翻译：掺杂纳米结构
公开(公告)号：US08685877B2
公开(公告)日：2014-04-01
申请号：US11960653
申请日：2007-12-19
申请人： Francesca Iacopi , Philippe M. Vereecken
发明人： Francesca Iacopi , Philippe M. Vereecken
IPC分类号： B01J21/00 , B01J23/04 , B01J21/02 , B01J27/00 , B01J27/02 , B01J23/06
CPC分类号： C30B29/06 , C30B11/12 , C30B29/60 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02603 , H01L21/02645 , H01L21/02653
摘要： A catalyst particle for use in growth of elongated nanostructures, such as e.g. nanowires, is provided. The catalyst particle comprises a catalyst compound for catalyzing growth of an elongated nanostructure comprising a nanostructure material without substantially dissolving in the nanostructure material and at least one dopant element for doping the elongated nanostructure during growth by substantially completely dissolving in the nanostructure material. A method for forming an elongated nanostructure, e.g. nanowire, on a substrate using the catalyst particle is also provided. The method allows controlling dopant concentration in the elongated nanostructures, e.g. nanowires, and allows elongated nanostructures with a low dopant concentration of lower than 1017 atoms/cm3 to be obtained.
摘要翻译：用于细长纳米结构生长的催化剂颗粒，例如，纳米线。催化剂颗粒包括用于催化包含纳米结构材料的细长纳米结构的生长的催化剂化合物，其基本上不溶解在纳米结构材料中，以及至少一种掺杂元素，用于在生长期间通过基本上完全溶解在纳米结构材料中来掺杂细长纳米结构。形成细长纳米结构的方法，例如。还提供了使用催化剂颗粒的基板上的纳米线。该方法允许控制细长纳米结构中的掺杂剂浓度，例如。纳米线，并且允许获得具有低于1017原子/ cm3的低掺杂剂浓度的细长纳米结构。

2. 发明授权

US07718531B2 Method for forming catalyst nanoparticles for growing elongated nanostructures 有权
标题翻译：用于形成用于生长细长纳米结构的催化剂纳米颗粒的方法
公开(公告)号：US07718531B2
公开(公告)日：2010-05-18
申请号：US12146885
申请日：2008-06-26
申请人： Aleksandar Radisic , Philippe M. Vereecken
发明人： Aleksandar Radisic , Philippe M. Vereecken
IPC分类号： H01L21/44
CPC分类号： B01J35/0013 , B01J23/75 , B01J37/06 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C01B32/18 , H01L21/76876 , H01L21/76879 , H01L51/0002 , H01L51/0048 , H01L2221/1094
摘要： Preferred embodiments provide a method for forming at least one catalyst nanoparticle on at least one sidewall of a three-dimensional structure on a main surface of a substrate, the main surface lying in a plane and the sidewall of the three-dimensional structure lying in a plane substantially perpendicular to the plane of the main surface of the substrate. The method comprises obtaining a three-dimensional structure on the main surface, the three-dimensional structure comprising catalyst nanoparticles embedded in a non-catalytic matrix and selectively removing at least part of the non-catalytic matrix at the sidewalls of the three-dimensional structure to thereby expose at least one catalyst nanoparticle.
摘要翻译：优选的实施方案提供了一种在基材的主表面上的三维结构的至少一个侧壁上形成至少一种催化剂纳米颗粒的方法，主表面位于平面中，三维结构的侧壁位于基本上垂直于基板的主表面的平面。该方法包括在主表面上获得三维结构，三维结构包括嵌入在非催化基质中的催化剂纳米颗粒，并且在三维结构的侧壁选择性地除去至少部分非催化性基体从而暴露至少一种催化剂纳米颗粒。

3. 发明申请

US20090014878A1 STRUCTURE AND METHOD OF FORMING ELECTRODEPOSITED CONTACTS 有权
标题翻译：形成电沉积联系的结构和方法
公开(公告)号：US20090014878A1
公开(公告)日：2009-01-15
申请号：US12130381
申请日：2008-05-30
申请人： Cyril Cabral, JR. , Hariklia Deligianni , Randolph F. Knarr , Sandra G. Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe M. Vereecken
发明人： Cyril Cabral, JR. , Hariklia Deligianni , Randolph F. Knarr , Sandra G. Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe M. Vereecken
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/2885 , H01L21/76843 , H01L21/76846 , H01L21/76877 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.
摘要翻译：一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的硅化物或锗化物层，例如钴和/或镍; 接触层，其包含位于介电层顶部并且在空腔内并与底部的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。

4. 发明申请

US20080217181A1 FREE STANDING SINGLE-CRYSTAL NANOWIRE GROWTH BY ELECTRO-CHEMICAL DEPOSITION 有权
标题翻译：通过电化学沉积法实现单晶纳米线生长
公开(公告)号：US20080217181A1
公开(公告)日：2008-09-11
申请号：US11746023
申请日：2007-05-08
申请人： Geoffroy Hautier , Philippe M. Vereecken
发明人： Geoffroy Hautier , Philippe M. Vereecken
IPC分类号： C25D1/04
CPC分类号： C25D5/022 , C25D3/54 , C25D17/001 , C25D17/007
摘要： The present invention relates to a method for obtaining monocrystalline or single crystal nanowires. Said nanowires are grown in a pattern making use of electro-chemical deposition techniques. Most preferred, the electrolytic bath is based on chlorides and has an acidic pH. Single element as well as combinations of two elements nanowires can be grown. Depending on the element properties the obtained nanowire can have metallic (conductive) or semi-metallic (semi-conductive) properties. The observed nanowire growth presents an unusual behavior compared to the classical nanowire template-assisted growth where a cap is formed as soon as the metal grows out of the pattern. Under given conditions of bath composition and potential (current) settings the nanowires grow out of the pattern up to a few microns without any significant lateral overgrowth.
摘要翻译：本发明涉及一种获得单晶或单晶纳米线的方法。所述纳米线以使用电化学沉积技术的图案生长。最优选地，电解浴基于氯化物并具有酸性pH。单个元素以及两个元素的组合可以生长纳米线。取决于元素性质，所得纳米线可具有金属（导电）或半金属（半导电）性质。观察到的纳米线生长与经典的纳米线模板辅助生长相比是一个不寻常的行为，其中一旦金属从图案中生长出来，形成盖。在给定的浴组成和潜在（电流）设置条件下，纳米线从图案长出几微米，没有任何明显的横向过度生长。

5. 发明申请

US20080142894A1 GATE STACK ENGINEERING BY ELECTROCHEMICAL PROCESSING UTILIZING THROUGH-GATE-DIELECTRIC CURRENT FLOW 有权
标题翻译：通过电化学处理利用栅极电介质电流流动的栅极堆叠工程
公开(公告)号：US20080142894A1
公开(公告)日：2008-06-19
申请号：US12040350
申请日：2008-02-29
申请人： Philippe M. Vereecken , Veeraraghavan S. Basker , Cyril Cabral , Emanuel I. Cooper , Hariklia Deligianni , Martin M. Frank , Rajarao Jammy , Vamsi Krishna Paruchuri , Katherine L. Saenger , Xiaoyan Shao
发明人： Philippe M. Vereecken , Veeraraghavan S. Basker , Cyril Cabral , Emanuel I. Cooper , Hariklia Deligianni , Martin M. Frank , Rajarao Jammy , Vamsi Krishna Paruchuri , Katherine L. Saenger , Xiaoyan Shao
IPC分类号： H01L27/088 , H01L29/423
CPC分类号： H01L21/2885 , C25D3/50 , C25D5/02 , C25D5/024 , C25D5/54 , C25D7/123 , C25D9/04 , C25F3/14 , H01L21/28079 , H01L21/28114 , H01L21/76885 , H01L29/513 , H01L29/517 , H01L29/78648
摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.
摘要翻译：提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或熔化。还提供了利用电介质电流流动的电介质电化学修饰方法。

6. 发明授权

US07112851B2 Field effect transistor with electroplated metal gate 失效
公开(公告)号：US07112851B2
公开(公告)日：2006-09-26
申请号：US11228269
申请日：2005-10-26
申请人： Katherine L. Saenger , Cyril Cabral, Jr. , Hariklia Deligianni , Caliopi Andricacos, legal representative , Philippe M. Vereecken , Emanuel I. Cooper
发明人： Panayotis C. Andricacos, deceased
IPC分类号： H01L29/786
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/66621 , H01L29/7834
摘要： Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

7. 发明授权

US07008871B2 Selective capping of copper wiring 有权
标题翻译：铜线选择性封盖
公开(公告)号：US07008871B2
公开(公告)日：2006-03-07
申请号：US10611931
申请日：2003-07-03
申请人： Panayotis C. Andricacos , Shyng-Tsong Chen , John M. Cotte , Hariklia Deligianni , Mahadevaiyer Krishnan , Wei-Tsu Tseng , Philippe M. Vereecken
发明人： Panayotis C. Andricacos , Shyng-Tsong Chen , John M. Cotte , Hariklia Deligianni , Mahadevaiyer Krishnan , Wei-Tsu Tseng , Philippe M. Vereecken
IPC分类号： H01L21/44
CPC分类号： H01L21/76846 , H01L21/2885 , H01L21/6708 , H01L21/76849 , H01L21/7685 , H01L21/76874 , H01L21/76883
摘要： Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.
摘要翻译：通过在衬垫材料的存在下使用选择性蚀刻和/或选择性电镀选择性地封盖铜来制造图案化的铜结构。提供了用于解决在电蚀和/或电镀过程中作为电解质增加的电阻路径从晶片边缘向内流动的问题的装置。

8. 发明申请

US20100075486A1 FORMATION OF SINGLE CRYSTAL SEMICONDUCTOR NANOWIRES 有权
标题翻译：形成单晶半导体纳米颗粒
公开(公告)号：US20100075486A1
公开(公告)日：2010-03-25
申请号：US12490189
申请日：2009-06-23
申请人： Philippe M. Vereecken
发明人： Philippe M. Vereecken
IPC分类号： H01L21/20
CPC分类号： C30B29/60 , B82Y10/00 , B82Y30/00 , C30B1/023 , C30B29/605 , H01L29/0665 , H01L29/0673 , H01L29/0676 , Y10S977/762 , Y10S977/813
摘要： A method is provided for growing mono-crystalline nanostructures onto a substrate. The method comprises at least the steps of first providing a pattern onto a main surface of the substrate wherein said pattern has openings extending to the surface of the substrate, providing a metal into the openings of the pattern on the exposed main surface, at least partly filling the opening with amorphous material, and then annealing the substrate at temperatures between 300° C. and 1000° C. thereby transforming the amorphous material into a mono-crystalline material by metal mediated crystallization to form the mono-crystalline nanostructure.
摘要翻译：提供了一种将单晶纳米结构生长到基底上的方法。该方法至少包括以下步骤：首先在衬底的主表面上提供图案，其中所述图案具有延伸到衬底表面的开口，在暴露的主表面上的图案的开口中提供金属，至少部分地用无定形材料填充开口，然后在300℃和1000℃之间的温度下退火衬底，从而通过金属介导的结晶将无定形材料转化为单晶材料，以形成单晶纳米结构。

9. 发明申请

US20080284036A1 STRUCTURE FOR OPTIMIZING FILL IN SEMICONDUCTOR FEATURES DEPOSITED BY ELECTROPLATING 审中-公开
标题翻译：电镀沉积半导体特性优化结构
公开(公告)号：US20080284036A1
公开(公告)日：2008-11-20
申请号：US12180203
申请日：2008-07-25
申请人： Conal E. Murray , Philippe M. Vereecken
发明人： Conal E. Murray , Philippe M. Vereecken
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L21/76838 , C25D17/007 , C25D17/10 , H01L21/2885
摘要： A structure and process are provided that are capable of reducing the occurrence of discontinuities within the metallization, such as voiding or seams, formed during electroplating at the edges of semiconductor metallization arrays. The structure includes a metallization bar located around the periphery of the array. The process employs the structure during electroplating.
摘要翻译：提供了一种结构和工艺，其能够减少在金属化期间的不连续性的发生，例如在半导体金属化阵列的边缘处的电镀期间形成的空隙或接缝。该结构包括位于阵列周边周围的金属化棒。该方法在电镀期间采用该结构。

10. 发明授权

US07446040B2 Structure for optimizing fill in semiconductor features deposited by electroplating 失效
标题翻译：用于优化通过电镀沉积的半导体特征填充的结构
公开(公告)号：US07446040B2
公开(公告)日：2008-11-04
申请号：US11330537
申请日：2006-01-12
申请人： Conal E. Murray , Philippe M. Vereecken
发明人： Conal E. Murray , Philippe M. Vereecken
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , C25D17/007 , C25D17/10 , H01L21/2885
摘要： A structure and process are provided that are capable of reducing the occurrence of discontinuities within the metallization, such as voiding or seams, formed during electroplating at the edges of semiconductor metallization arrays. The structure includes a metallization bar located around the periphery of the array. The process employs the structure during electroplating.
摘要翻译：提供了一种结构和工艺，其能够减少在金属化期间的不连续性的发生，例如在半导体金属化阵列的边缘处的电镀期间形成的空隙或接缝。该结构包括位于阵列周边周围的金属化棒。该方法在电镀期间采用该结构。

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