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1. 发明授权

US07814485B2 System and method for adaptive power management based on processor utilization and cache misses 有权
标题翻译：基于处理器利用率和高速缓存未命中的自适应电源管理系统和方法
公开(公告)号：US07814485B2
公开(公告)日：2010-10-12
申请号：US11007098
申请日：2004-12-07
申请人： Bryan C Morgan , Premanand Sakarda , Priya N Vaidya , Yi Ge , Zhou Gao , Swee-chin Pang , Manoj I Thadani , Canhui Yuan
发明人： Bryan C Morgan , Premanand Sakarda , Priya N Vaidya , Yi Ge , Zhou Gao , Swee-chin Pang , Manoj I Thadani , Canhui Yuan
IPC分类号： G06F9/46 , G06F1/00
CPC分类号： G06F1/3228 , G06F1/324 , Y02D10/126
摘要： A processing system may include a performance monitoring unit (PMU), a machine accessible medium, and a processor responsive to the PMU and the machine accessible medium. Instructions encoded in the machine accessible medium, when executed by the processor, may determine whether performance details for the processing system should be collected, based at least in part on a predetermined monitoring policy for the processing system. The instructions may generate performance data for the processing system, based at least in part on data obtained from the PMU. The instructions may determine whether the processing system should be reconfigured, based at least in part on the performance data and a power policy profile for the processing system. The instructions may automatically adjust power consumption of the processing system by using the PMU to reconfigure the processing system. Other embodiments are described and claimed.
摘要翻译：处理系统可以包括性能监视单元（PMU），机器可访问介质和响应于PMU和机器可访问介质的处理器。在机器可访问介质中编码的指令在由处理器执行时可以至少部分地基于用于处理系统的预定监视策略来确定是否应该收集处理系统的性能细节。该指令可以至少部分地基于从PMU获得的数据来生成处理系统的性能数据。所述指令可以至少部分地基于所述处理系统的性能数据和功率策略简档来确定所述处理系统是否应被重新配置。该指令可以通过使用PMU重新配置处理系统来自动调整处理系统的功耗。描述和要求保护其他实施例。

2. 发明授权

US07346787B2 System and method for adaptive power management 有权
标题翻译：自适应电源管理系统和方法
公开(公告)号：US07346787B2
公开(公告)日：2008-03-18
申请号：US11006917
申请日：2004-12-07
申请人： Priya N Vaidya , Premanand Sakarda , Bryan C Morgan , Yi Ge
发明人： Priya N Vaidya , Premanand Sakarda , Bryan C Morgan , Yi Ge
IPC分类号： G06F1/00
CPC分类号： G06F1/3228 , G06F1/324 , Y02D10/126
摘要： A disclosed method involves initializing a performance profiler of a processing system. The performance profiler may include performance profile parameters for a power management policy for the processing system. The method also involves retrieving performance metrics for the processing system from a performance monitoring unit (PMU) of the processing system, in response to a determination that performance details should be collected. A current performance state of the processing system may be determined, based at least in part on the performance profile parameters and the performance metrics from the PMU. The current performance state may then be communicated to a policy manager of the processing system. Other embodiments are disclosed and claimed.
摘要翻译：所公开的方法涉及初始化处理系统的性能分析器。性能分析器可以包括用于处理系统的电源管理策略的性能简档参数。该方法还涉及从处理系统的性能监视单元（PMU）检索处理系统的性能指标，以响应于应该收集性能细节的确定。可以至少部分地基于来自PMU的性能简档参数和性能度量来确定处理系统的当前性能状态。可以将当前的性能状态传送给处理系统的策略管理器。公开和要求保护其他实施例。

3. 发明授权

US08402293B2 Power management in electronic systems 有权
公开(公告)号：US08402293B2
公开(公告)日：2013-03-19
申请号：US13171157
申请日：2011-06-28
申请人： Bryan C. Morgan , Priya N. Vaidya , Premanand Sakarda , Marlon A. Moncrieffe
发明人： Bryan C. Morgan , Priya N. Vaidya , Premanand Sakarda , Marlon A. Moncrieffe
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.

4. 发明申请

US20090172432A1 Power management in electronic systems 有权
标题翻译：电子系统中的电源管理
公开(公告)号：US20090172432A1
公开(公告)日：2009-07-02
申请号：US12006064
申请日：2007-12-28
申请人： Bryan C. Morgan , Priya N. Vaidya , Premanand Sakarda , Marlon A. Moncrieffe
发明人： Bryan C. Morgan , Priya N. Vaidya , Premanand Sakarda , Marlon A. Moncrieffe
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.
摘要翻译：在一个实施例中，电子设备包括耦合到处理器的至少一个处理器和计算机可读介质，并且包括编码在计算机可读介质中的逻辑指令，其中当在处理系统中执行时，指令使处理系统执行操作包括在电子系统中初始化直接存储器访问分析器，其中所述直接存储器访问耦合到所述电子系统中的策略管理器，测量所述电子系统的至少一个存储器消耗特性，将所述至少一个存储器消耗特性传达到电子系统的策略管理器，并且使用至少一个存储器消耗特性来调整电子系统的功率状态。

5. 发明申请

US20140108830A1 POWER MANAGEMENT IN ELECTRONIC SYSTEMS 有权
标题翻译：电子系统中的电源管理
公开(公告)号：US20140108830A1
公开(公告)日：2014-04-17
申请号：US13847036
申请日：2013-03-19
申请人： Bryan C. Morgan , Priya N. Vaidya , Premanand Sakarda , Marlon A. Moncrieffe
发明人： Bryan C. Morgan , Priya N. Vaidya , Premanand Sakarda , Marlon A. Moncrieffe
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3246 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.
摘要翻译：在一个实施例中，电子设备包括耦合到处理器的至少一个处理器和计算机可读介质，并且包括编码在计算机可读介质中的逻辑指令，其中当在处理系统中执行时，指令使处理系统执行操作包括在电子系统中初始化直接存储器访问分析器，其中所述直接存储器访问耦合到所述电子系统中的策略管理器，测量所述电子系统的至少一个存储器消耗特性，将所述至少一个存储器消耗特性传达到电子系统的策略管理器，并且使用至少一个存储器消耗特性来调整电子系统的功率状态。

6. 发明申请

US20120166844A1 POWER MANAGEMENT IN ELECTRONIC SYSTEMS 有权
标题翻译：电子系统中的电源管理
公开(公告)号：US20120166844A1
公开(公告)日：2012-06-28
申请号：US13171157
申请日：2011-06-28
申请人： BRYAN C. MORGAN , PRIYA N. VAIDYA , PREMANAND SAKARDA , MARLON A. MONCRIEFFE
发明人： BRYAN C. MORGAN , PRIYA N. VAIDYA , PREMANAND SAKARDA , MARLON A. MONCRIEFFE
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.
摘要翻译：在一个实施例中，电子设备包括耦合到处理器的至少一个处理器和计算机可读介质，并且包括编码在计算机可读介质中的逻辑指令，其中当在处理系统中执行时，指令使处理系统执行操作包括在电子系统中初始化直接存储器访问分析器，其中所述直接存储器访问耦合到所述电子系统中的策略管理器，测量所述电子系统的至少一个存储器消耗特性，将所述至少一个存储器消耗特性传达到电子系统的策略管理器，并且使用至少一个存储器消耗特性来调整电子系统的功率状态。

7. 发明授权

US07971084B2 Power management in electronic systems 有权
标题翻译：电子系统中的电源管理
公开(公告)号：US07971084B2
公开(公告)日：2011-06-28
申请号：US12006064
申请日：2007-12-28
申请人： Bryan C. Morgan , Priya N. Vaidya , Premanand Sakarda , Marlon A. Moncrieffe
发明人： Bryan C. Morgan , Priya N. Vaidya , Premanand Sakarda , Marlon A. Moncrieffe
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.
摘要翻译：在一个实施例中，电子设备包括耦合到处理器的至少一个处理器和计算机可读介质，并且包括编码在计算机可读介质中的逻辑指令，其中当在处理系统中执行时，指令使处理系统执行操作包括在电子系统中初始化直接存储器访问分析器，其中所述直接存储器访问耦合到所述电子系统中的策略管理器，测量所述电子系统的至少一个存储器消耗特性，将所述至少一个存储器消耗特性传达到电子系统的策略管理器，并且使用至少一个存储器消耗特性来调整电子系统的功率状态。

8. 发明授权

US07266646B2 Least mean square dynamic cache-locking 有权
标题翻译：最小均方动态缓存锁定
公开(公告)号：US07266646B2
公开(公告)日：2007-09-04
申请号：US11501490
申请日：2006-08-08
申请人： Priya N. Vaidya , Moinul H. Khan
发明人： Priya N. Vaidya , Moinul H. Khan
IPC分类号： G06F12/12
CPC分类号： G06F12/126 , G06F12/0875
摘要： A dynamic cache-locking algorithm may determine the most frequently used function(s) and the number of cache lines that should be locked into the instruction cache embedded into a processor. By evaluating the dynamic cache-locking algorithm, a determination may be made to lock an optimal amount of functions that correspond to a given, limited amount of instruction cache.
摘要翻译：动态高速缓存锁定算法可以确定应该被锁定到嵌入到处理器中的指令高速缓存中的最常用的功能和高速缓存线的数量。通过评估动态高速缓存锁定算法，可以确定锁定与给定的有限量的指令高速缓存相对应的最佳功能量。

9. 发明授权

US07159096B2 Method and apparatus to perform memory management 有权
公开(公告)号：US07159096B2
公开(公告)日：2007-01-02
申请号：US10816268
申请日：2004-03-31
申请人： Moinul H. Khan , Priya N. Vaidya
发明人： Moinul H. Khan , Priya N. Vaidya
IPC分类号： G06F12/08 , G06F12/06
CPC分类号： G06F12/1027
摘要： A method and apparatus to perform memory management are described.

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