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1. 发明授权

US08402293B2 Power management in electronic systems 有权
公开(公告)号：US08402293B2
公开(公告)日：2013-03-19
申请号：US13171157
申请日：2011-06-28
申请人： Bryan C. Morgan , Priya N. Vaidya , Premanand Sakarda , Marlon A. Moncrieffe
发明人： Bryan C. Morgan , Priya N. Vaidya , Premanand Sakarda , Marlon A. Moncrieffe
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.

2. 发明申请

US20090172432A1 Power management in electronic systems 有权
标题翻译：电子系统中的电源管理
公开(公告)号：US20090172432A1
公开(公告)日：2009-07-02
申请号：US12006064
申请日：2007-12-28
申请人： Bryan C. Morgan , Priya N. Vaidya , Premanand Sakarda , Marlon A. Moncrieffe
发明人： Bryan C. Morgan , Priya N. Vaidya , Premanand Sakarda , Marlon A. Moncrieffe
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.
摘要翻译：在一个实施例中，电子设备包括耦合到处理器的至少一个处理器和计算机可读介质，并且包括编码在计算机可读介质中的逻辑指令，其中当在处理系统中执行时，指令使处理系统执行操作包括在电子系统中初始化直接存储器访问分析器，其中所述直接存储器访问耦合到所述电子系统中的策略管理器，测量所述电子系统的至少一个存储器消耗特性，将所述至少一个存储器消耗特性传达到电子系统的策略管理器，并且使用至少一个存储器消耗特性来调整电子系统的功率状态。

3. 发明申请

US20140108830A1 POWER MANAGEMENT IN ELECTRONIC SYSTEMS 有权
标题翻译：电子系统中的电源管理
公开(公告)号：US20140108830A1
公开(公告)日：2014-04-17
申请号：US13847036
申请日：2013-03-19
申请人： Bryan C. Morgan , Priya N. Vaidya , Premanand Sakarda , Marlon A. Moncrieffe
发明人： Bryan C. Morgan , Priya N. Vaidya , Premanand Sakarda , Marlon A. Moncrieffe
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3246 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.
摘要翻译：在一个实施例中，电子设备包括耦合到处理器的至少一个处理器和计算机可读介质，并且包括编码在计算机可读介质中的逻辑指令，其中当在处理系统中执行时，指令使处理系统执行操作包括在电子系统中初始化直接存储器访问分析器，其中所述直接存储器访问耦合到所述电子系统中的策略管理器，测量所述电子系统的至少一个存储器消耗特性，将所述至少一个存储器消耗特性传达到电子系统的策略管理器，并且使用至少一个存储器消耗特性来调整电子系统的功率状态。

4. 发明授权

US07971084B2 Power management in electronic systems 有权
标题翻译：电子系统中的电源管理
公开(公告)号：US07971084B2
公开(公告)日：2011-06-28
申请号：US12006064
申请日：2007-12-28
申请人： Bryan C. Morgan , Priya N. Vaidya , Premanand Sakarda , Marlon A. Moncrieffe
发明人： Bryan C. Morgan , Priya N. Vaidya , Premanand Sakarda , Marlon A. Moncrieffe
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.
摘要翻译：在一个实施例中，电子设备包括耦合到处理器的至少一个处理器和计算机可读介质，并且包括编码在计算机可读介质中的逻辑指令，其中当在处理系统中执行时，指令使处理系统执行操作包括在电子系统中初始化直接存储器访问分析器，其中所述直接存储器访问耦合到所述电子系统中的策略管理器，测量所述电子系统的至少一个存储器消耗特性，将所述至少一个存储器消耗特性传达到电子系统的策略管理器，并且使用至少一个存储器消耗特性来调整电子系统的功率状态。

5. 发明授权

US07266646B2 Least mean square dynamic cache-locking 有权
标题翻译：最小均方动态缓存锁定
公开(公告)号：US07266646B2
公开(公告)日：2007-09-04
申请号：US11501490
申请日：2006-08-08
申请人： Priya N. Vaidya , Moinul H. Khan
发明人： Priya N. Vaidya , Moinul H. Khan
IPC分类号： G06F12/12
CPC分类号： G06F12/126 , G06F12/0875
摘要： A dynamic cache-locking algorithm may determine the most frequently used function(s) and the number of cache lines that should be locked into the instruction cache embedded into a processor. By evaluating the dynamic cache-locking algorithm, a determination may be made to lock an optimal amount of functions that correspond to a given, limited amount of instruction cache.
摘要翻译：动态高速缓存锁定算法可以确定应该被锁定到嵌入到处理器中的指令高速缓存中的最常用的功能和高速缓存线的数量。通过评估动态高速缓存锁定算法，可以确定锁定与给定的有限量的指令高速缓存相对应的最佳功能量。

6. 发明授权

US07159096B2 Method and apparatus to perform memory management 有权
公开(公告)号：US07159096B2
公开(公告)日：2007-01-02
申请号：US10816268
申请日：2004-03-31
申请人： Moinul H. Khan , Priya N. Vaidya
发明人： Moinul H. Khan , Priya N. Vaidya
IPC分类号： G06F12/08 , G06F12/06
CPC分类号： G06F12/1027
摘要： A method and apparatus to perform memory management are described.

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