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1. 发明授权

US08356143B1 Prefetch mechanism for bus master memory access 有权
标题翻译：总线主机内存访问预取机制
公开(公告)号：US08356143B1
公开(公告)日：2013-01-15
申请号：US10971608
申请日：2004-10-22
申请人： Ravi P. Bulusu , Subir K. Ghosh
发明人： Ravi P. Bulusu , Subir K. Ghosh
IPC分类号： G06F12/00
CPC分类号： G06F13/1605 , G06F13/1673
摘要： A system and method for optimizing memory bus bandwidth, is achieved by utilization of the memory bus, either by utilizing the idle time of the memory bus, or by prioritizing prefetch requests to exploit the bank structure of the external memory. When a bus master of the memory bus makes a request to access a particular line in a memory device, the memory controller generates a request for accessing a line next to the current line that is requested by the bus master. Data corresponding to the next line is retrieved from the memory device and stored in the memory-controller when the memory bus is idle. The stored data may be served to a bus master upon request for the data. However, the memory bus is not engaged when the data stored in the memory controller is served. Therefore idle time of the memory bus is utilized.
摘要翻译：通过利用存储器总线的空闲时间，或通过优先处理预取请求以利用外部存储器的存储体结构来实现利用存储器总线来实现用于优化存储器总线带宽的系统和方法。当存储器总线的总线主机请求访问存储器件中的特定线路时，存储器控制器产生访问总线主机请求的当前行旁边的线路的请求。当存储器总线空闲时，从存储器件检索对应于下一行的数据并存储在存储器控制器中。所存储的数据可以根据数据的请求被提供给总线主机。然而，当存储在存储器控制器中的数据被提供时，存储器总线不被接合。因此利用存储器总线的空闲时间。

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