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1. 发明授权

US08356143B1 Prefetch mechanism for bus master memory access 有权
标题翻译：总线主机内存访问预取机制
公开(公告)号：US08356143B1
公开(公告)日：2013-01-15
申请号：US10971608
申请日：2004-10-22
申请人： Ravi P. Bulusu , Subir K. Ghosh
发明人： Ravi P. Bulusu , Subir K. Ghosh
IPC分类号： G06F12/00
CPC分类号： G06F13/1605 , G06F13/1673
摘要： A system and method for optimizing memory bus bandwidth, is achieved by utilization of the memory bus, either by utilizing the idle time of the memory bus, or by prioritizing prefetch requests to exploit the bank structure of the external memory. When a bus master of the memory bus makes a request to access a particular line in a memory device, the memory controller generates a request for accessing a line next to the current line that is requested by the bus master. Data corresponding to the next line is retrieved from the memory device and stored in the memory-controller when the memory bus is idle. The stored data may be served to a bus master upon request for the data. However, the memory bus is not engaged when the data stored in the memory controller is served. Therefore idle time of the memory bus is utilized.
摘要翻译：通过利用存储器总线的空闲时间，或通过优先处理预取请求以利用外部存储器的存储体结构来实现利用存储器总线来实现用于优化存储器总线带宽的系统和方法。当存储器总线的总线主机请求访问存储器件中的特定线路时，存储器控制器产生访问总线主机请求的当前行旁边的线路的请求。当存储器总线空闲时，从存储器件检索对应于下一行的数据并存储在存储器控制器中。所存储的数据可以根据数据的请求被提供给总线主机。然而，当存储在存储器控制器中的数据被提供时，存储器总线不被接合。因此利用存储器总线的空闲时间。

2. 发明授权

US5900016A System for using a cache memory with a write-back architecture 失效
标题翻译：使用具有回写架构的高速缓冲存储器的系统
公开(公告)号：US5900016A
公开(公告)日：1999-05-04
申请号：US825888
申请日：1997-04-02
申请人： Subir K. Ghosh
发明人： Subir K. Ghosh
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0804
摘要： A computer system includes a microprocessor, a cache memory, main memory and supporting logic. The supporting logic includes cache control logic that determines whether an access to memory results in a hit to the cache for dirty or clean data. When a write to the cache results in a hit to clean data, the bus cycle is enlarged in order to set a dirty bit associated with the write data. The bus cycle is enlarged by requesting the processor to refrain from commencing a new bus cycle or driving a new memory address.
摘要翻译：计算机系统包括微处理器，高速缓冲存储器，主存储器和支持逻辑。支持逻辑包括高速缓存控制逻辑，其确定对存储器的访问是否导致对高速缓存的命中以用于脏的或干净的数据。当写入高速缓存导致清除数据的命中时，总线周期被放大，以便设置与写入数据相关联的脏位。通过请求处理器禁止开始新的总线周期或驱动新的存储器地址来扩大总线周期。

3. 发明授权

US5426739A Local bus - I/O Bus Computer Architecture 失效
标题翻译：本地总线 - I / O总线计算机体系结构
公开(公告)号：US5426739A
公开(公告)日：1995-06-20
申请号：US961773
申请日：1992-10-14
申请人： Fong Lu Lin , Subir K. Ghosh , Win Chen , Jhyping Shaw , Chen-Yung V. Chen
发明人： Fong Lu Lin , Subir K. Ghosh , Win Chen , Jhyping Shaw , Chen-Yung V. Chen
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4027
摘要： In a computer system, one or more ISA connector sockets is replaced by a connector structure which carries both ISA signals and local bus signals. The connector structure is arranged such that a standard ISA accessory card may be inserted, in which case only ISA signals are coupled to or from the card. "Local bus" accessory cards may also be designed for insertion into such a connector, and these cards may connect to one or more signal lines of the local bus either additionally or instead of connections made to the ISA bus. By physical or other means, ISA accessory cards are prevented from unintentional contact with connector contacts which are coupled to local bus signal lines. The connector structure may advantageously comprise an EISA-type connector socket.
摘要翻译：在计算机系统中，一个或多个ISA连接器插座由承载ISA信号和本地总线信号的连接器结构代替。连接器结构被布置成使得可以插入标准的ISA附件卡，在这种情况下，只有ISA信号耦合到卡或从卡耦合。 “本地总线”附件卡也可以被设计成用于插入到这样的连接器中，并且这些卡可以附加地或连接到ISA总线的连接而连接到本地总线的一个或多个信号线。通过物理或其他方式，防止ISA附件卡与连接到本地总线信号线的连接器触点意外接触。连接器结构可以有利地包括EISA型连接器插座。

4. 发明授权

US5469555A Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system 失效
标题翻译：自适应回写方法和装置，其中高速缓存系统以用于基于高速缓存的微处理器系统的回写和写通模式的组合操作
公开(公告)号：US5469555A
公开(公告)日：1995-11-21
申请号：US889740
申请日：1992-05-28
申请人： Subir K. Ghosh , Dipankar Bhattacharya
发明人： Subir K. Ghosh , Dipankar Bhattacharya
IPC分类号： G06F12/02 , G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0804 , G06F12/0888 , G06F12/0891 , G06F12/0215
摘要： Method and apparatus for reducing the access time required to write to memory and read from memory in a computer system having a cache-based memory. A dynamic determination is made on a cycle by cycle basis of whether data should be written to the cache with a dirty bit asserted, or the data should be written to both the cache and main memory. The write-through method is chosen where the write-through method is approximately as fast as the write-back method. Where the write-back method is substantially faster than the write-through method, the write-back method is chosen.
摘要翻译：用于减少在具有基于高速缓存的存储器的计算机系统中写入存储器和从存储器读取所需的访问时间的方法和装置。逐周期地进行动态确定，是否应该将数据写入高速缓存中，否则应将脏位置为有效，或将数据写入高速缓存和主存储器。选择写通方法，其中直写方法大约与回写方法一样快。如果写回方法比直写方法快得多，则选择回写方法。

5. 发明授权

US5463759A Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system 失效
公开(公告)号：US5463759A
公开(公告)日：1995-10-31
申请号：US419736
申请日：1995-04-10
申请人： Subir K. Ghosh , Dipankar Bhattacharya
发明人： Subir K. Ghosh , Dipankar Bhattacharya
IPC分类号： G06F12/02 , G06F12/08 , G06F12/00 , G06F12/12 , G06F13/00
CPC分类号： G06F12/0804 , G06F12/0888 , G06F12/0891 , G06F12/0215
摘要： Method and apparatus for reducing the access time required to write to memory and read from memory in a computer system having a cache-based memory. A dynamic determination is made on a cycle by cycle basis of whether data should be written to the cache with a dirty bit asserted, or the data should be written to both the cache and main memory. The write-through method is chosen where the write-through method is approximately as fast as the write-back method. Where the write-back method is substantially faster than the write-through method, the write-back method is chosen.

6. 发明授权

US5768624A Method and apparatus for employing ping-pong buffering with one level deep buffers for fast DRAM access 失效
标题翻译：用于采用乒乓缓冲的方法和装置，其具有用于快速DRAM访问的一级深缓冲器
公开(公告)号：US5768624A
公开(公告)日：1998-06-16
申请号：US608108
申请日：1996-02-28
申请人： Subir K. Ghosh
发明人： Subir K. Ghosh
IPC分类号： G06F13/16 , G06F13/00
CPC分类号： G06F13/1673
摘要： A memory access chip set includes a data buffer chip and a system controller chip. The data buffer chip contains storage elements that buffer data values transferred between a memory and either the host data bus or the peripheral bus. In one aspect, the storage elements are transparent latches, and not master/slave flip-flops. In another aspect, the storage elements are operated asynchronously. In another aspect, the storage elements are exactly two levels deep (additional accommodations are made in the case of data busses having mismatched widths). The arrangement of storage elements is such that only a single control pin is required on the data buffer chip to enable them, and only a single input pin (plus, in some cases, a clock input pin) for externally coordinating outputs from the storage elements for synchronous transfer over the destination bus. The system controller chip generates both the input control signal for the data buffer chip and CAS# for the memory, such that propagation delay variations in the system controller chip for the input control signal are substantially similar those in the system controller chip for CAS#.
摘要翻译：存储器存取芯片组包括数据缓冲器芯片和系统控制器芯片。数据缓冲器芯片包含缓存在存储器与主机数据总线或外设总线之间传输的数据值的存储元件。在一个方面，存储元件是透明锁存器，而不是主/从触发器。另一方面，存储元件是异步操作的。在另一方面，存储元件恰好是两个深度级（在数据总线具有不匹配的宽度的情况下进行额外的调节）。存储元件的布置使得在数据缓冲器芯片上仅需要一个控制引脚来使它们能够使用，并且只有一个输入引脚（在某些情况下加上一个时钟输入引脚）用于外部协调存储元件的输出用于通过目标总线进行同步传输。系统控制器芯片产生用于数据缓冲器芯片的输入控制信号和用于存储器的CAS＃，使得用于输入控制信号的系统控制器芯片中的传播延迟变化与用于CAS＃的系统控制器芯片中的传播延迟变化基本相似。

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