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1. 发明授权

US07785482B2 Method of making an ignition device 有权
标题翻译：制造点火装置的方法
公开(公告)号：US07785482B2
公开(公告)日：2010-08-31
申请号：US11296247
申请日：2005-12-07
申请人： Kanakasabapathi Subramanian , Richard Joseph Saia , Aaron Jay Knobloch , David Joseph Najewicz , Nicholas Okruch, Jr.
发明人： Kanakasabapathi Subramanian , Richard Joseph Saia , Aaron Jay Knobloch , David Joseph Najewicz , Nicholas Okruch, Jr.
IPC分类号： H01B13/00
CPC分类号： C23C8/40 , C23C8/12 , F23Q7/22 , F24C3/103
摘要： A method of manufacturing an ignition device is provided. The method includes patterning a plurality of resistors on a membrane to form heating elements and thermally isolating the heating elements from an external environment via a cavity disposed adjacent to the heating elements.
摘要翻译：提供一种制造点火装置的方法。该方法包括在膜上图形化多个电阻器以形成加热元件并且通过邻近加热元件设置的空腔将加热元件与外部环境热隔离。

2. 发明申请

US20090028491A1 INTERCONNECT STRUCTURE 审中-公开
标题翻译：互连结构
公开(公告)号：US20090028491A1
公开(公告)日：2009-01-29
申请号：US11828550
申请日：2007-07-26
申请人： Raymond Albert Fillion , Kevin Matthew Durocher , Richard Joseph Saia , Charles Gerard Woychik
发明人： Raymond Albert Fillion , Kevin Matthew Durocher , Richard Joseph Saia , Charles Gerard Woychik
IPC分类号： G02B6/12 , H01L23/48
CPC分类号： H01L23/13 , H01L23/49811 , H01L23/49827 , H01L23/49833 , H01L24/24 , H01L24/82 , H01L2224/04105 , H01L2224/18 , H01L2224/76155 , H01L2224/82102 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15312 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3511 , H01L2924/00
摘要： An interconnect structure includes an insulative web having a first surface and a second surface; a logic device secured to the second surface of the insulative web; a frame panel assembly including a frame base having a first surface and a second surface, a first frame insulative layer disposed between the frame base first surface and the insulative web second surface, an aperture extending through the frame base and first frame insulative layer, wherein at least a portion of the logic device is disposed within the aperture, and a first frame connector disposed between a first electrically conductive layer located on the frame base first surface, and a second electrically conductive layer located on a surface of the first frame insulative layer; a device connector disposed between an I/O contact on a surface of the logic device and a third electrical conductor located on a surface of the insulative web; and an insulative layer connector that is disposed between the third electrical conductor located on a surface of the insulative web and the second electrically conductive layer located on a surface of the first frame insulative layer.
摘要翻译：互连结构包括具有第一表面和第二表面的绝缘网; 固定在绝缘网的第二表面上的逻辑装置; 框架面板组件，包括具有第一表面和第二表面的框架基座，设置在框架基部第一表面和绝缘网片第二表面之间的第一框架绝缘层，延伸穿过框架基部和第一框架绝缘层的孔，其中所述逻辑器件的至少一部分设置在所述孔内，并且设置在位于所述框架基底第一表面上的第一导电层之间的第一框架连接器和位于所述第一框架绝缘层的表面上的第二导电层 ; 设置在所述逻辑器件的表面上的I / O触点和位于所述绝缘网的表面上的第三电导体之间的器件连接器; 以及绝缘层连接器，其设置在位于所述绝缘片的表面上的所述第三电导体和位于所述第一框架绝缘层的表面上的所述第二导电层之间。

3. 发明授权

US06790703B2 Apparatus for aligning die to interconnect metal on flex substrate 有权
标题翻译：用于对准芯片以在柔性基板上互连金属的装置
公开(公告)号：US06790703B2
公开(公告)日：2004-09-14
申请号：US10199296
申请日：2002-07-22
申请人： Richard Joseph Saia , Kevin Matthew Durocher , James Wilson Rose , Leonard Richard Douglas
发明人： Richard Joseph Saia , Kevin Matthew Durocher , James Wilson Rose , Leonard Richard Douglas
IPC分类号： H01L2158
CPC分类号： H01L24/76 , H01L23/5389 , H01L24/19 , H01L24/82 , H01L2223/54426 , H01L2224/04105 , H01L2224/32225 , H01L2224/8314 , H01L2224/83192 , H01L2224/92144 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/01087 , H01L2924/12042 , H01L2924/14 , H01L2924/1423 , Y10T29/49131 , H01L2924/00
摘要： A method and process sequence for accurately aligning (die to interconnect metal on flex substrate such as polyimide flex is described. A mask for via formation is first patterned in a metal layer on the bottom surface of the flex substrate. Die attach means such as die attach adhesive is then applied to the top side of flex substrate. The bond pads on die are locally, adaptively aligned to the patterned metal via mask on the flex with high accuracy. Vias down to the die bond pads are then created by either plasma etching or excimer laser ablation through the existing aligned metal mask on the flex substrate, and interconnect metal is then deposited, patterned and etched. As a result of this process, the flex metal interconnect artwork does not have to be customized for each die misplacement using “adaptive lithography”. Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost. The method is compatible with the projected designs of the next generation die which will have bond pads on the order of 40um in size.
摘要翻译：描述了用于精确对准（模具与柔性基板上的互连金属如聚酰亚胺柔性）的方法和工艺顺序，首先在柔性基板的底表面上的金属层中对通孔形成用掩模进行图案化，然后将附着的粘合剂施加到柔性基板的顶侧，芯片上的接合焊盘以高精度局部地适应性地与柔性上的图案化金属通孔掩模对准，然后通过等离子体蚀刻或准分子激光烧蚀通过柔性基板上的现有对准的金属掩模，然后沉积，图案化和蚀刻互连金属。作为该过程的结果，柔性金属互连图案不需要针对每个管芯错位进行定制，适应光刻“，低成本商业光刻设备可用于加工，减少资本设备和加工成本，该方法与p 下一代模具的抛光设计将具有大小为40um的接合垫。

4. 发明授权

US06548329B1 Amorphous hydrogenated carbon hermetic structure fabrication method 失效
标题翻译：无定形氢化碳密封结构制造方法
公开(公告)号：US06548329B1
公开(公告)日：2003-04-15
申请号：US09561870
申请日：2000-05-01
申请人： Richard Joseph Saia , Kevin Matthew Durocher , James Wilson Rose
发明人： Richard Joseph Saia , Kevin Matthew Durocher , James Wilson Rose
IPC分类号： H01L2156
CPC分类号： H01L23/49894 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/00
摘要： A hard layer of amorphous hydrogenated carbon (DLC) overlies a polymer film structure and a plurality of soft layers of DLC alternate with a plurality of hard layers of DLC over the barrier base to form a corrosion resistant structure. The polymer film structure and a circuit chip can be elements of a circuit module. The DLC and the polymer film structure can have vias extending to contact pads, and a pattern of electrical conductors can extend through the vias to the contact pads. In one embodiment the DLC forms a hermetic (and therefore corrosion resistant) seal over the polymer film structure.
摘要翻译：无定形氢化碳（DLC）的硬层覆盖聚合物膜结构，并且DLC的多个软层与阻挡基底上的多个DLC硬层交替以形成耐腐蚀结构。聚合物膜结构和电路芯片可以是电路模块的元件。 DLC和聚合物膜结构可以具有延伸到接触焊盘的通孔，并且电导体的图案可以延伸穿过通孔到接触焊盘。在一个实施方案中，DLC在聚合物膜结构上形成密封（因此是耐腐蚀的）密封。

5. 发明授权

US5963791A Silicon carbide MOSFET having self-aligned gate structure and method of fabrication 失效
标题翻译：具有自对准栅极结构的碳化硅MOSFET和制造方法
公开(公告)号：US5963791A
公开(公告)日：1999-10-05
申请号：US900442
申请日：1997-07-25
申请人： Dale Marius Brown , Richard Joseph Saia , John Adam Edmond , John Williams Palmour
发明人： Dale Marius Brown , Richard Joseph Saia , John Adam Edmond , John Williams Palmour
IPC分类号： H01L21/04 , H01L29/24 , H01L29/423 , H01L21/00
CPC分类号： H01L29/1608 , H01L29/66068 , H01L29/78 , Y10S438/931
摘要： A SiC MOSFET having a self-aligned gate structure is fabricated upon a monocrystalline substrate layer, such as a p type conductivity .alpha.6H silicon carbide (SiC) substrate. An SiC n+ type conductivity layer is epitaxially grown on the substrate layer. A steep-walled groove is etched through the n+ SiC layer and partially into the p SiC layer at a location on the substrate where a MOSFET gate structure is desired. Subsequently, a thin layer of silicon dioxide and a layer of gate metal are successively deposited over the entire structure. The gate metal layer is deposited with sufficient thickness to substantially fill the groove. A layer of photoresist is applied to the entire surface of the gate metal layer. The photoresist and the underlying gate metal are then reactive ion etched down to the oxide layer, leaving gate metal remaining only in the groove. The gate metal and oxide layer form the self-aligned gate structure wherein the walls of the groove are automatically aligned with the edges of drain and source regions that are formed on either side of the groove.
摘要翻译：具有自对准栅极结构的SiC MOSFET在单晶衬底层（例如p型导电性α6H碳化硅（SiC））衬底上制造。在衬底层上外延生长SiC n +型导电层。通过n + SiC层蚀刻陡壁凹槽，并且在需要MOSFET栅极结构的衬底上的位置处部分地蚀刻到p SiC层中。随后，在整个结构上依次沉积二氧化硅薄层和栅极金属层。栅极金属层被沉积有足够的厚度以基本上填充凹槽。将光致抗蚀剂层施加到栅极金属层的整个表面。然后将光致抗蚀剂和下面的栅极金属反应离子蚀刻到氧化物层，留下栅极金属仅在沟槽中。栅极金属和氧化物层形成自对准栅极结构，其中沟槽的壁自动地与形成在槽的任一侧上的漏极和源极区域的边缘对准。

6. 发明授权

US5736448A Fabrication method for thin film capacitors 失效
标题翻译：薄膜电容器的制造方法
公开(公告)号：US5736448A
公开(公告)日：1998-04-07
申请号：US566616
申请日：1995-12-04
申请人： Richard Joseph Saia , Kevin Matthew Durocher , Bernard Gorowitz
发明人： Richard Joseph Saia , Kevin Matthew Durocher , Bernard Gorowitz
IPC分类号： H01G4/33 , H01L23/498 , H01L23/538 , H01L27/01 , H01L21/20
CPC分类号： H01L23/5383 , H01L23/49894 , H01L27/016 , H01L2924/0002
摘要： A capacitor is fabricated on a base surface by applying a first pattern of electrical conductors (a first capacitor plate) over the base surface with an outer surface of the first pattern of electrical conductors including molybdenum. A first hard portion of a capacitor dielectric layer including amorphous hydrogenated carbon is deposited over the first capacitor plate and the base surface, a soft portion of the capacitor dielectric layer is deposited over the first hard portion, and a second hard portion of the capacitor dielectric layer is deposited over the soft portion. The deposition of the soft portion occurs at a lower bias voltage than the deposition of the first and second hard portions. A second pattern of electrical conductors (a second capacitor plate) is applied over the capacitor dielectric layer which is then patterned. A polymer layer is applied over the first and second capacitor plates, and two vias are formed, a first via extending to the first capacitor plate and a second via extending to the second capacitor plate. An electrode-coupling pattern of electrical conductors is applied over the polymer layer, a first portion extending into the first via and a second portion extending into the second via. Deposition of the capacitor dielectric layer can include using a methylethylketone precursor. Additional capacitor dielectric layers and plates having staggered via landing pads can be layered to increase the capacitance.
摘要翻译：通过在基底表面上施加电导体（第一电容器板）的第一图案，使第一电导体图案包括钼的外表面，在基底表面上制造电容器。包括无定形氢化碳的电容器电介质层的第一硬部分沉积在第一电容器板和基底表面上，电容器电介质层的软部分沉积在第一硬部分上，电容器电介质的第二硬部分层沉积在软部分上。软部分的沉积在比第一和第二硬部分的沉积更低的偏压下发生。将电导体（第二电容器板）的第二图案施加在电容器电介质层上，然后将其图案化。将聚合物层施加在第一和第二电容器板上，形成两个通孔，延伸到第一电容器板的第一通孔和延伸到第二电容器板的第二通孔。电导体的电极耦合图案施加在聚合物层上，第一部分延伸到第一通孔中，第二部分延伸到第二通孔中。电容器介电层的沉积可以包括使用甲基乙基酮前体。具有交错通孔接地焊盘的附加电容器电介质层和板可以被层叠以增加电容。

7. 发明授权

US5726463A Silicon carbide MOSFET having self-aligned gate structure 失效
标题翻译：具有自对准栅极结构的碳化硅MOSFET
公开(公告)号：US5726463A
公开(公告)日：1998-03-10
申请号：US925823
申请日：1992-08-07
申请人： Dale Marius Brown , Richard Joseph Saia , John Adam Edmond , John Williams Palmour
发明人： Dale Marius Brown , Richard Joseph Saia , John Adam Edmond , John Williams Palmour
IPC分类号： H01L21/04 , H01L29/24 , H01L29/423 , H01L31/0256 , H01L29/76 , H01L31/0312
CPC分类号： H01L29/1608 , H01L29/66068 , H01L29/78 , Y10S438/931
摘要： A SiC MOSFET having a self-aligned gate structure is fabricated upon a monocrystalline substrate layer, such as a p type conductivity .alpha.6H silicon carbide (SiC) substrate. An SiC n+ type conductivity layer, epitaxially grown on the substrate layer, includes a steep-walled groove etched through the n+ SiC layer and partially into the p SiC layer. The groove is lined with a thin layer of silicon dioxide which extends onto the n+ type conductivity layer. A filling of gate metal over the layer of silicon dioxide is contained entirely in the groove. The silicon dioxide layer includes a first window extending to the filling of gate metal in the groove, and second and third windows extending to the n+ type conductivity layer on either side of the groove, respectively. A gate contact extends through the first window to the filling of gate metal in the groove while drain and source contacts extend through the second and third window, respectively, to make contact with the n+ type conductivity layer in drain and source regions on either side of the groove.
摘要翻译：具有自对准栅极结构的SiC MOSFET在单晶衬底层（例如p型导电性α6H碳化硅（SiC））衬底上制造。在衬底层上外延生长的SiC n +型导电层包括通过n + SiC层蚀刻并部分地进入p SiC层的陡壁沟槽。凹槽衬有一层二氧化硅，其延伸到n +型导电层上。栅极金属在二氧化硅层上的填充完全包含在槽中。二氧化硅层包括延伸到槽中的栅极金属填充物的第一窗口，以及分别延伸到沟槽两侧的n +型导电层的第二和第三窗口。栅极接触件延伸穿过第一窗口以填充沟槽中的栅极金属，而漏极和源极触点分别延伸穿过第二和第三窗口，以与第二和第三窗口中的漏极和源极区域中的n +型导电层接触，凹槽

8. 发明授权

US5699234A Stacking of three dimensional high density interconnect modules with metal edge contacts 失效
标题翻译：堆叠具有金属边缘触点的三维高密度互连模块
公开(公告)号：US5699234A
公开(公告)日：1997-12-16
申请号：US790045
申请日：1997-01-28
申请人： Richard Joseph Saia , Bernard Gorowitz , Kevin Matthew Durocher
发明人： Richard Joseph Saia , Bernard Gorowitz , Kevin Matthew Durocher
IPC分类号： H01L21/98 , H01L23/538 , H01L25/065 , H05K1/03 , H05K1/14 , H05K3/40 , H05K3/46 , H01R23/70 , H01L23/055
CPC分类号： H01L25/50 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L25/0652 , H05K1/144 , H05K3/403 , H01L2224/24225 , H01L2224/24227 , H01L2224/2919 , H01L2224/8384 , H01L2225/06513 , H01L2225/06551 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H05K1/0306 , H05K2201/09581 , H05K3/4611 , H05K3/4629 , H05K3/4685 , Y10T29/49126
摘要： A method for fabricating a stack of circuit modules includes providing a plurality of substrates having module interconnection layers. Each of the substrates has a circuit chip with chip pads positioned therein and an electrically conductive feed-through line extending from a first surface of the substrate to a second surface of the substrate with the first surface being perpendicular to the second surface. Each of the module interconnection layers is situated over a respective first surface of each of the substrates and includes a module dielectric layer having module vias therein and a module pattern of electrical conductors extending through the module vias to couple the selected chip pads to the feed-through line. The plurality of substrates are stacked. A side interconnection layer is applied over a side surface including the second surfaces of the substrates. The side interconnection layer includes a side dielectric layer having side vias therein aligned with predetermined ones of the feed-through lines and a side pattern of electrical conductors extending through the side vias.
摘要翻译：一种用于制造电路模块堆叠的方法包括提供具有模块互连层的多个基板。每个基板具有其中设置有芯片焊盘的电路芯片，以及导电的馈通线，其从基板的第一表面延伸到基板的第二表面，其中第一表面垂直于第二表面。每个模块互连层位于每个基板的相应的第一表面上，并且包括其中具有模块通孔的模块介电层和延伸穿过模块通孔的电导体的模块图案，以将所选择的芯片焊盘耦合到馈送 - 通过线。堆叠多个基板。侧面互连层被施加在包括基板的第二表面的侧表面上。侧面互连层包括侧面介电层，其侧面通孔与预定的馈通线对准，并且电导体的侧面图案延伸穿过侧面通孔。

9. 发明授权

US5652559A Method of micromachining electromagnetically actuated current switches with polyimide reinforcement seals, and switches produced thereby 失效
标题翻译：具有聚酰亚胺加强密封的微电机驱动电流开关的微加工方法以及由此产生的开关
公开(公告)号：US5652559A
公开(公告)日：1997-07-29
申请号：US626311
申请日：1996-04-01
申请人： Richard Joseph Saia , Mario Ghezzo , Bharat Sampath Kumar Bagepalli , Kevin Matthew Durocher
发明人： Richard Joseph Saia , Mario Ghezzo , Bharat Sampath Kumar Bagepalli , Kevin Matthew Durocher
IPC分类号： B81B3/00 , H01H50/00 , H01H51/22
CPC分类号： B81B7/0012 , H01H50/005 , B81B2201/018 , Y10T29/49105
摘要： An insulating layer with at least one via is provided over a metal plate. A sacrificial layer is applied over a portion of the insulating layer so that the sacrificial layer extends into the via. A metal bridge having at least one opening is provided over a portion of the sacrificial layer and a portion of the insulating layer so that the metal bridge extends over the via and the opening is situated adjacent a portion of the sacrificial layer. A reinforcing seal layer with a well is provided over the metal bridge so that the well is situated adjacent to at least a portion of the opening. The sacrificial layer is then removed.
摘要翻译：具有至少一个通孔的绝缘层设置在金属板的上方。牺牲层施加在绝缘层的一部分上，使得牺牲层延伸到通孔中。在牺牲层的一部分和绝缘层的一部分上设置具有至少一个开口的金属桥，使得金属桥在通孔上方延伸，并且开口位于牺牲层的一部分附近。在金属桥上提供了具有井的增强密封层，使得井位于与开口的至少一部分相邻的位置。然后去除牺牲层。

10. 发明授权

US08604612B2 Chip attach adhesive to facilitate embedded chip build up and related systems and methods 有权
标题翻译：芯片附着胶，便于嵌入式芯片的建立及相关系统及方法
公开(公告)号：US08604612B2
公开(公告)日：2013-12-10
申请号：US12389060
申请日：2009-02-19
申请人： Richard Joseph Saia , Thomas Bert Gorczyca
发明人： Richard Joseph Saia , Thomas Bert Gorczyca
IPC分类号： H01L23/12 , H01L21/58 , C09J163/00 , C08G59/68
CPC分类号： H01L24/83 , C08G59/226 , C08G59/68 , C09J5/00 , C09J163/00 , C09J2203/326 , C09J2463/00 , G03F7/038 , H01L24/19 , H01L24/29 , H01L24/82 , H01L2224/04105 , H01L2224/2413 , H01L2224/2919 , H01L2224/82039 , H01L2224/83192 , H01L2224/8385 , H01L2224/92144 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/18162 , H01L2924/3512 , H01L2924/00
摘要： Present embodiments are directed to an adhesive and method for assembling a chip package. The adhesive may be used to couple a chip to a substrate, and the adhesive may include an epoxy-based dielectric material, an epoxy resin, a photoacid generator, an antioxidant, and a cold catalyst corresponding to the photoacid generator.
摘要翻译：本实施例涉及用于组装芯片封装的粘合剂和方法。粘合剂可以用于将芯片耦合到基底，并且粘合剂可以包括对应于光致酸产生剂的环氧基介电材料，环氧树脂，光致酸产生剂，抗氧化剂和冷催化剂。

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