专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10169500B2 Critical path delay prediction 有权
公开(公告)号：US10169500B2
公开(公告)日：2019-01-01
申请号：US13204812
申请日：2011-08-08
申请人： Margaret R. Charlebois , Rashmi D. Chatty , Christopher D. Hanudel , Robert D. Herzl , David W. Milton , Clarence R. Ogilvie , Matthew P. Szafir , Tad J. Wilder
发明人： Margaret R. Charlebois , Rashmi D. Chatty , Christopher D. Hanudel , Robert D. Herzl , David W. Milton , Clarence R. Ogilvie , Matthew P. Szafir , Tad J. Wilder
IPC分类号： G06F19/00 , G06F17/50
摘要： Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator.

2. 发明申请

US20140028365A1 RING OSCILLATOR 有权
标题翻译：戒指振荡器
公开(公告)号：US20140028365A1
公开(公告)日：2014-01-30
申请号：US13558498
申请日：2012-07-26
申请人： Margaret R. Charlebois , Rashmi D. Chatty , Christopher D. Hanudel , Robert D. Herzl , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Matthew P. Szafir , Tad J. Wilder
发明人： Margaret R. Charlebois , Rashmi D. Chatty , Christopher D. Hanudel , Robert D. Herzl , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Matthew P. Szafir , Tad J. Wilder
IPC分类号： H03H11/26
CPC分类号： H03K3/0315
摘要： Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided.
摘要翻译：本发明的方面提供了一种电路结构，其自动监测多个环形振荡器并且动态地选择最快或最慢的环形振荡器用于反馈到多个环形振荡器中。在一个实施例中，电路包括：多个延迟元件，每个延迟元件与环形振荡器相关联; 用于接收每个延迟元件的输出的第一逻辑门; 第二逻辑门，用于接收每个延迟元件的输出; 以及多路复用器，用于接收第一逻辑门的输出和第二逻辑门的输出并选择输出之一，其中多路复用器的选择基于多路复用器的输出。为了选择最快的环形振荡器，提供了第二个多路复用器。

3. 发明授权

US08341588B2 Semiconductor layer forming method and structure 有权
标题翻译：半导体层形成方法和结构
公开(公告)号：US08341588B2
公开(公告)日：2012-12-25
申请号：US12897021
申请日：2010-10-04
申请人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： G06F15/04 , G06F17/50
CPC分类号： G06F17/5068 , G06F2217/72
摘要： A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures. The second semiconductor device comprises the additional structure layer located within the second insertion point location.
摘要翻译：一种形成和电气结构的方法。该方法包括确定第一半导体器件需要工程改变顺序（ECO）。确定实现ECO所需的附加结构层。选择用于将附加结构层插入第一半导体器件内的第一插入点位置。第一插入点位置与用于第二半导体器件的设计中的第二插入点位置相关联。根据第一ECO产生第二半导体器件。第二半导体器件包括第二结构。第二结构包括与第一半导体器件中的第一结构相同的结构。第二结构形成在第二半导体器件内的与包含第一结构的第一半导体器件中的位置相关联的位置。第二半导体器件包括位于第二插入点位置内的附加结构层。

4. 发明申请

US20120167022A1 METHOD AND DEVICE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BLOCK LOGIC FOR EASY ENGINEERING CHANGES 审中-公开
标题翻译：用于识别和实现灵活逻辑块逻辑的方法和设备，用于轻松的工程变更
公开(公告)号：US20120167022A1
公开(公告)日：2012-06-28
申请号：US13410386
申请日：2012-03-02
申请人： Robert D. HERZL , Robert S. HORTON , Kenneth A. LAURICELLA , David W. MILTON , Clarence R. OGILVIE , Paul M. SCHANELY , Nitin SHARMA , Tad J. WILDER , Charles B. WINN
发明人： Robert D. HERZL , Robert S. HORTON , Kenneth A. LAURICELLA , David W. MILTON , Clarence R. OGILVIE , Paul M. SCHANELY , Nitin SHARMA , Tad J. WILDER , Charles B. WINN
IPC分类号： G06F9/45
CPC分类号： G06F17/5045
摘要： A chip design methodology and an integrated circuit chip. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).
摘要翻译：芯片设计方法和集成电路芯片。该方法包括识别工程可变逻辑，并用灵活的逻辑块（FLB）替换所识别的工程可变逻辑。

5. 发明授权

US08060845B2 Minimizing impact of design changes for integrated circuit designs 有权
标题翻译：最大限度地减少设计变更对集成电路设计的影响
公开(公告)号：US08060845B2
公开(公告)日：2011-11-15
申请号：US12173222
申请日：2008-07-15
申请人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method is provided for updating an existing netlist to reflect a design change. A register transfer level (RTL) design incorporating the design change and the existing netlist are provided to a synthesis tool. The existing netlist is set to a read-only condition to prevent a change to the existing netlist. The design and the read-only existing netlist are processed with the synthesis tool reusing logic structures from the read-only existing netlist by performing an optimization of the design and the read-only existing netlist with an objective to minimize the design space. The optimization is constrained by the read-only existing netlist. A result is generated by the synthesis tool including the existing netlist and a new portion of a netlist reflecting the design change.
摘要翻译：提供了一种用于更新现有网表以反映设计变更的方法。将设计更改和现有网表的注册传输级别（RTL）设计提供给综合工具。现有的网表设置为只读条件，以防止更改现有的网表。通过执行设计优化和只读现有网表的综合工具对来自只读现有网表的逻辑结构进行重用，设计和只读现有网表被处理，目的是最小化设计空间。优化受只读现有网表约束。综合工具产生的结果包括现有网表和反映设计变更的网表的新部分。

6. 发明授权

US06539522B1 Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs 失效
标题翻译：开发可重用软件的方法，用于片上系统集成电路设计的有效验证
公开(公告)号：US06539522B1
公开(公告)日：2003-03-25
申请号：US09494907
申请日：2000-01-31
申请人： Robert J. Devins , Paul G. Ferro , Robert D. Herzl , Mark E. Kautzman , Kenneth A. Mahler , David W. Milton
发明人： Robert J. Devins , Paul G. Ferro , Robert D. Herzl , Mark E. Kautzman , Kenneth A. Mahler , David W. Milton
IPC分类号： G06F1750
CPC分类号： G01R31/318357 , G06F17/5022
摘要： A method for developing re-usable software for the efficient verification of system-on-chip (SOC) integrated circuit designs. The verification software is used to generate and apply test cases to stimulate components of a SOC design (“cores”) in simulation; the results are observed and used to de-bug the design. The software is hierarchical, implementing a partition between upper-level test application code which generates test cases and verifies results, and low-level device driver code which interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations. Test application and supporting low-level device driver pairs are used and re-used to test their corresponding component cores throughout the SOC development process, by creating higher-level test control programs which control selected combinations of the already-developed test application and device driver programs to test combinations of SOC components. The method provides for the efficient verification of SOC designs and, consequently, a reduced time-to-market for SOC products, because as the verification software is developed and stored, it becomes possible to test increasingly complex core combinations by creating relatively few high-level test programs which re-use already-existing lower-level software. Ultimately, the task of verifying a complex SOC design may be simplified to developing a single chip-specific test program which selects from already-existing test application, device driver and test control programs to perform a realistic test of a chip-specific combination of cores.
摘要翻译：一种用于开发用于片上系统（SOC）集成电路设计的有效验证的可重用软件的方法。验证软件用于生成和应用测试用例，以刺激模拟中SOC设计（“核心”）的组件; 观察结果并用于对设计进行设计。该软件是分级的，实现生成测试用例的上级测试应用程序代码和验证结果之间的分区，以及与正在模拟的内核接口的低级设备驱动程序代码，以应用由上级代码生成的测试用例在硬件层面的操作。测试应用程序和支持低级设备驱动程序对被使用并重新用于在SOC开发过程中测试其相应的组件核心，通过创建更高级别的测试控制程序来控制已经开发的测试应用程序和设备驱动程序的选定组合测试SOC组件组合的程序。该方法提供SOC设计的有效验证，从而缩短了SOC产品的上市时间，因为随着验证软件的开发和存储，可以通过创建相对较少的高可用性测试来测试日益复杂的核心组合，重新使用已经存在的低级软件的级别测试程序。最终，可以简化验证复杂SOC设计的任务，以开发单个芯片特定的测试程序，该测试程序从已经存在的测试应用程序，设备驱动程序和测试控制程序中进行选择，以执行芯片特定的内核组合的现实测试。

7. 发明授权

US08181148B2 Method for identifying and implementing flexible logic block logic for easy engineering changes 有权
标题翻译：识别和实现灵活逻辑块逻辑以方便工程变更的方法
公开(公告)号：US08181148B2
公开(公告)日：2012-05-15
申请号：US12014240
申请日：2008-01-15
申请人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： G06F15/04 , G06F17/50
CPC分类号： G06F17/5045
摘要： A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).
摘要翻译：芯片设计方法。该方法包括识别工程可变逻辑，并用灵活的逻辑块（FLB）替换所识别的工程可变逻辑。

8. 发明授权

US08141028B2 Structure for identifying and implementing flexible logic block logic for easy engineering changes 有权
标题翻译：用于识别和实现灵活逻辑块逻辑的结构，便于工程变更
公开(公告)号：US08141028B2
公开(公告)日：2012-03-20
申请号：US12054835
申请日：2008-03-25
申请人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： G06F15/04 , G06F17/50
CPC分类号： G06F17/5045
摘要： A design structure for identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.
摘要翻译：用于识别工程可变逻辑的设计结构，以及用灵活的逻辑块（FLB）替换所识别的工程可变逻辑。该设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。

9. 发明申请

US20080133206A1 METHOD OF SWITCHING EXTERNAL MODELS IN AN AUTOMATED SYSTEM-ON-CHIP INTEGRATED CIRCUIT DESIGN VERIFICATION SYSTEM 有权
标题翻译：在自动系统集成电路设计验证系统中切换外部模型的方法
公开(公告)号：US20080133206A1
公开(公告)日：2008-06-05
申请号：US11969991
申请日：2008-01-07
申请人： Robert J. Devins , Robert D. Herzl , David W. Milton
发明人： Robert J. Devins , Robert D. Herzl , David W. Milton
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A system and method for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.
摘要翻译：提供一种用于验证集成电路设计的系统和方法。该系统包括：连接到一个或多个I / O核心的I / O控制器，集成电路设计的I / O核心部分; 具有用于选择性地将一个或多个所述I / O核心连接到相应的I / O驱动器模型的开关的外部存储器映射测试装置; 用于在I / O控制器和开关之间传送信号的总线; 以及用于控制开关的测试操作系统。

10. 发明授权

US5361368A Cross interrogate synchronization mechanism including logic means and delay register 失效
标题翻译：交叉询问同步机制包括逻辑装置和延迟寄存器
公开(公告)号：US5361368A
公开(公告)日：1994-11-01
申请号：US755236
申请日：1991-09-05
申请人： Robert D. Herzl , Linda L. Quinn , Russell E. Schroter
发明人： Robert D. Herzl , Linda L. Quinn , Russell E. Schroter
IPC分类号： G06F13/00 , G06F12/08 , G06F13/14 , G06F13/368 , G06F15/16 , G06F15/177 , G06F13/40 , G06F13/18
CPC分类号： G06F12/0828 , G06F12/0822 , G06F13/14
摘要： A mechanism prioritizes cross interrogate requests between multiple requestors in a multi-processor system where the delay due to cable length interconnecting requestors results in requests not being received within one machine cycle. Local and remote cross interrogate (XI) requests are latched up in storage control element (SCE) temporary registers before being prioritized. The local request is staged in a local delay register. The local request is selected from the local delay register by synchronization control logic, instead of the temporary register, when the remote request is issued one cycle earlier than the local request, or when both local and remote requests are issued at the same time, but the remote requests is from a master SCE. The staging of the local requests can be extended to multiple cycles, corresponding to the length of the cables between SCEs.
摘要翻译：一种机制优先考虑多处理器系统中的多个请求者之间的交叉询问请求，其中由于电缆长度互连请求者引起的延迟导致在一个机器周期内未被接收的请求。本地和远程交叉询问（XI）请求被优先锁存在存储控制元件（SCE）临时寄存器中。本地请求在本地延迟寄存器中进行。本地请求是通过同步控制逻辑从本地延迟寄存器中选择的，而不是临时寄存器，当远程请求比本地请求提前一个周期发送时，或当本地和远程请求同时发出时，远程请求来自主SCE。本地请求的分段可以扩展到多个周期，对应于SCE之间的电缆长度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式