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1. 发明申请

US20180143905A1 NETWORK-AWARE CACHE COHERENCE PROTOCOL ENHANCEMENT 审中-公开
公开(公告)号：US20180143905A1
公开(公告)日：2018-05-24
申请号：US15358318
申请日：2016-11-22
申请人： Advanced Micro Devices, Inc.
发明人： David A. Roberts , Ehsan Fatehi
IPC分类号： G06F12/0815 , G06F12/084 , G06F12/0817 , G06F13/16
CPC分类号： G06F12/0815 , G06F12/0822 , G06F12/0824 , G06F12/0826 , G06F12/084 , G06F13/1615 , G06F2212/1024 , G06F2212/314 , G06F2212/502 , G06F2212/621
摘要： A non-uniform memory access system includes several nodes that each have one or more processors, caches, local main memory, and a local bus that connects a node's processor(s) to its memory. The nodes are coupled to one another over a collection of point-to-point interconnects, thereby permitting processors in one node to access data stored in another node. Memory access time for remote memory takes longer than local memory because remote memory accesses have to travel across a communications network to arrive at the requesting processor. In some embodiments, inter-cache and main-memory-to-cache latencies are measured to determine whether it would be more efficient to satisfy memory access requests using cached copies stored in caches of owning nodes or from main memory of home nodes.

2. 发明授权

US09823730B2 Power management of cache duplicate tags 有权
公开(公告)号：US09823730B2
公开(公告)日：2017-11-21
申请号：US14793778
申请日：2015-07-08
申请人： Apple Inc.
发明人： Muditha Kanchana , Erik P. Machnicki
IPC分类号： G06F1/32 , G06F12/0813 , G06F12/0831 , G06F12/0817
CPC分类号： G06F1/3275 , G06F12/0813 , G06F12/0822 , G06F12/0831 , G06F2212/1016 , G06F2212/1028 , G06F2212/314 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A method and apparatus for power management of cache duplicate tags is disclosed. An IC includes a cache, a coherence circuit, and a duplicate tags memory that may store duplicates of the tags stored in the cache. The cache includes a number of ways that are separately and independently power controllable. The duplicate tags memory may be similarly organized, with portions that are power controllable separately and independently of others. The coherence circuit is also power controllable, and may be placed into a sleep mode when idle. The IC also includes a power management circuit. During operation, the cache may change power states and provide a corresponding indication to the power management circuit. Responsive to the indication, the power management circuit may awaken the coherence circuit if in a sleep state. The coherence circuit may then power manage the duplicate tags in accordance with the change in power state.

3. 发明申请

US20170315916A1 DIRECTORY MANAGEMENT METHOD, NODE CONTROLLER, AND SYSTEM 审中-公开
公开(公告)号：US20170315916A1
公开(公告)日：2017-11-02
申请号：US15581599
申请日：2017-04-28
申请人： Huawei Technologies Co., Ltd.
发明人： Yongbo Cheng , Kejia Lan , Chenghong He
IPC分类号： G06F12/0817 , G06F12/0811
CPC分类号： G06F12/0817 , G06F12/0811 , G06F12/0822 , G06F12/0831 , G06F2212/621
摘要： The present invention provide a directory management method including: receiving, by a first NC, a first data access request sent by a first processor on a local node; if the first NC determines that a first directory does not include a directory entry corresponding to a first access address and the first directory does not include an idle directory entry, clearing, by the first NC, directory content of a directory entry from the first directory; writing, by the first NC, directory content corresponding to the first data access request to the cleared directory entry; and if the first NC determines that a first snoop request is received, sending, by the first NC, a first snoop message to the processor on the local node.

4. 发明授权

US09740617B2 Hardware apparatuses and methods to control cache line coherence 有权
公开(公告)号：US09740617B2
公开(公告)日：2017-08-22
申请号：US14581097
申请日：2014-12-23
申请人： Intel Corporation
发明人： Samantika Sury , Simon Steely, Jr. , William Hasenplaugh , Joel Emer , David Webb
IPC分类号： G06F12/00 , G06F12/0831 , G06F12/0817
CPC分类号： G06F12/0833 , G06F12/0822 , G06F2212/283 , Y02D10/13
摘要： Methods and apparatuses to control cache line coherence are described. A hardware processor may include a first processor core with a cache to store a cache line, a second set of processor cores that each include a cache to store a copy of the cache line, and cache coherence logic to aggregate in a tag directory an acknowledgment message from each of the second set of processor cores in response to a request from the first processor core to modify the copy of the cache line in each of the second set of processor cores and send a consolidated acknowledgment message to the first processor core.

5. 发明授权

US09720834B2 Power saving for reverse directory 有权
公开(公告)号：US09720834B2
公开(公告)日：2017-08-01
申请号：US14966172
申请日：2015-12-11
申请人： Oracle International Corporation
发明人： Jinho Kwack , Joann Lam , Hoyeol Cho , Claire Ni
IPC分类号： G06F12/08 , G06F12/0817 , G06F12/0811 , G06F1/32 , G06F12/0808 , G06F12/0831
CPC分类号： G06F12/0822 , G06F1/3275 , G06F12/0808 , G06F12/0811 , G06F12/082 , G06F12/0831 , G06F12/0864 , G06F2212/1048 , G06F2212/283 , G06F2212/622 , Y02D10/13
摘要： Embodiments include systems and methods for improving power consumption characteristics of reverse directories in microprocessors. Some embodiments operate in context of multiprocessor semiconductors having cache hierarchies in which multiple higher-level caches share lower-level caches. Lower-level cache is coupled with reverse directories associated with respective ones of the higher-level caches. Each reverse directory can be segregated into two reverse sub-directories, one reverse sub-directory for relatively high-frequency accesses (e.g., updating “valid” and/or “private” information), and the other reverse sub-directories for relatively low-frequency accesses updating “index” and “way” information). During a write mode operation, when the reverse directories are updated, the write operation is performed only on the sub-directories having the entries invoked by the update, such that write operations can frequently consume only a fraction (e.g., halt) of the power of a conventional reverse directory write operation.

6. 发明申请

US20170109287A1 TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS 审中-公开
公开(公告)号：US20170109287A1
公开(公告)日：2017-04-20
申请号：US15393907
申请日：2016-12-29
申请人： Intel Corporation
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
IPC分类号： G06F12/0831 , G06F13/42 , G11C7/10 , G06F12/0811
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

7. 发明授权

US09552303B2 Method and system for maintaining release consistency in shared memory programming 有权
标题翻译：在共享存储器编程中保持释放一致性的方法和系统
公开(公告)号：US09552303B2
公开(公告)日：2017-01-24
申请号：US15218799
申请日：2016-07-25
申请人： Intel Corporation
发明人： Ravindra Babu Ganapathi , Hu Chen
IPC分类号： G06F3/06 , G06F12/08 , G06F12/0817 , G06F12/1009 , G06F12/128 , G06F13/16 , G06F12/10 , G06F12/12
CPC分类号： G06F12/1009 , G06F3/0614 , G06F3/0655 , G06F3/0671 , G06F12/08 , G06F12/0822 , G06F12/128 , G06F13/1663 , G06F2212/50 , G06F2212/6026 , G06F2212/621 , G06F2212/65 , G06F2212/657
摘要： A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in response to a page fault, initiating a transfer, from one processing unit to another, of data associated with more than one but less than all of the pages of shared memory.
摘要翻译：一种用于在具有多个处理单元的计算设备上维持共享存储器编程中的释放一致性的方法和系统包括响应于页面故障，从一个处理单元发起与多个处理单元相关联的数据的传输共享内存的所有页面。

8. 发明申请

US20170010655A1 Power Management of Cache Duplicate Tags 有权
标题翻译：缓存重复标签的电源管理
公开(公告)号：US20170010655A1
公开(公告)日：2017-01-12
申请号：US14793778
申请日：2015-07-08
申请人： Apple Inc.
发明人： Muditha Kanchana , Erik P. Machnicki
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F1/3275 , G06F12/0813 , G06F12/0822 , G06F12/0831 , G06F2212/1016 , G06F2212/1028 , G06F2212/314 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A method and apparatus for power management of cache duplicate tags is disclosed. An IC includes a cache, a coherence circuit, and a duplicate tags memory that may store duplicates of the tags stored in the cache. The cache includes a number of ways that are separately and independently power controllable. The duplicate tags memory may be similarly organized, with portions that are power controllable separately and independently of others. The coherence circuit is also power controllable, and may be placed into a sleep mode when idle. The IC also includes a power management circuit. During operation, the cache may change power states and provide a corresponding indication to the power management circuit. Responsive to the indication, the power management circuit may awaken the coherence circuit if in a sleep state. The coherence circuit may then power manage the duplicate tags in accordance with the change in power state.
摘要翻译：公开了一种缓存重复标签的电源管理方法和装置。 IC包括缓存，相干电路和可以存储存储在高速缓存中的标签的重复的重复标签存储器。高速缓存包括单独和独立的功率可控的多种方式。重复的标签存储器可以类似地组织，其中部分功率可以单独地并且独立于其它功能。相干电路也是功率可控的，并且可以在空闲时被置于睡眠模式。 IC还包括电源管理电路。在操作期间，高速缓存可以改变功率状态并且向电源管理电路提供相应的指示。响应于指示，如果处于睡眠状态，则电源管理电路可唤醒相干电路。然后，相干电路可以根据电源状态的变化来对重复标签进行电源管理。

9. 发明申请

US20160357671A1 SYSTEM AND METHOD FOR REMOVING DATA FROM PROCESSOR CACHES IN A DISTRIBUTED MULTI-PROCESSOR COMPUTER SYSTEM 有权
标题翻译：在分布式多处理器计算机系统中从处理器缓存中移除数据的系统和方法
公开(公告)号：US20160357671A1
公开(公告)日：2016-12-08
申请号：US15180322
申请日：2016-06-13
申请人： SILICON GRAPHICS INTERNATIONAL CORP.
发明人： Jeffrey S. Kuskin
IPC分类号： G06F12/0804 , G06F12/14 , G06F12/0842 , G06F12/0891 , G06F12/0813 , G06F12/0817
CPC分类号： G06F12/0804 , G06F12/0813 , G06F12/0822 , G06F12/0842 , G06F12/0891 , G06F12/1491
摘要： A processor (600) in a distributed shared memory multi-processor computer system (10) may initiate a flush request to remove data from its cache. A processor interface (24) receives the flush request and performs a snoop operation to determine whether the data is maintained in a one of the local processors (601) and whether the data has been modified. If the data is maintained locally and it has been modified, the processor interface (24) initiates removal of the data from the cache of the identified processor (601). The identified processor (601) initiates a writeback to a memory directory interface unit (24) associated with a home memory 17 for the data in order to preserve the modification to the data. If the data is not maintained locally or has not been modified, the processor interface (24) forwards the flush request to the memory directory interface unit (22). Memory directory interface unit (22) determines which remote processors within the system (10) have a copy of the data and forwards the flush request only to those identified processors. The identified processors then remove the data from their respective caches in response to the flush request. If an identified remote processor has modified data, the identified remote processor initiates a writeback to the memory directory interface unit (22) for preservation of the modified data.
摘要翻译：分布式共享存储器多处理器计算机系统（10）中的处理器（600）可以发起刷新请求以从其高速缓存中移除数据。处理器接口（24）接收刷新请求并执行窥探操作以确定数据是否保持在本地处理器（601）之一以及数据是否被修改。如果数据在本地维护并且已经被修改，则处理器接口（24）启动从所识别的处理器（601）的高速缓存中移除数据。所识别的处理器（601）发起与用于数据的归属存储器17相关联的存储器目录接口单元（24）的回写，以便保留对数据的修改。如果数据未在本地维护或未被修改，则处理器接口（24）将刷新请求转发到存储器目录接口单元（22）。存储器目录接口单元（22）确定系统（10）内的哪些远程处理器具有数据的副本，并将刷新请求仅转发到那些已识别的处理器。然后，所识别的处理器响应于刷新请求从其各自的高速缓存中移除数据。如果所识别的远程处理器具有修改的数据，则所识别的远程处理器发起对存储器目录接口单元（22）的回写以保存修改的数据。

10. 发明申请

US20160335197A1 METHOD AND SYSTEM FOR MAINTAINING RELEASE CONSISTENCY IN SHARED MEMORY PROGRAMMING 有权
标题翻译：在共享存储器编程中维护释放一致性的方法和系统
公开(公告)号：US20160335197A1
公开(公告)日：2016-11-17
申请号：US15218799
申请日：2016-07-25
申请人： Intel Corporation
发明人： Ravindra Babu Ganapathi , Hu Chen
IPC分类号： G06F12/1009 , G06F13/16 , G06F12/128
CPC分类号： G06F12/1009 , G06F3/0614 , G06F3/0655 , G06F3/0671 , G06F12/08 , G06F12/0822 , G06F12/128 , G06F13/1663 , G06F2212/50 , G06F2212/6026 , G06F2212/621 , G06F2212/65 , G06F2212/657
摘要： A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in response to a page fault, initiating a transfer, from one processing unit to another, of data associated with more than one but less than all of the pages of shared memory.
摘要翻译：一种用于在具有多个处理单元的计算设备上维持共享存储器编程中的释放一致性的方法和系统包括响应于页面故障，从一个处理单元发起与多个处理单元相关联的数据的传输共享内存的所有页面。

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