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1. 发明授权

US08947927B2 Gated diode memory cells 有权
标题翻译：门控二极管存储单元
公开(公告)号：US08947927B2
公开(公告)日：2015-02-03
申请号：US12512559
申请日：2009-07-30
申请人： Wing K. Luk , Robert H. Dennard
发明人： Wing K. Luk , Robert H. Dennard
IPC分类号： G11C11/405
CPC分类号： G11C11/405
摘要： A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).
摘要翻译：提供了门控二极管存储单元，其包括一个或多个晶体管，例如场效应晶体管（“FET”），以及与FET信号通信的门控二极管，使得门控二极管的栅极与源极信号通信第一FET的栅极，其中栅极二极管的栅极形成存储单元的一个端子，门控二极管的源极形成存储单元的另一个端子，第一FET的漏极与位线（“BL” “），并且第一FET的栅极与写入字线（”WLw“）进行信号通信，并且门控二极管的源极与读取字线（”WLr“）进行信号通信。

2. 发明授权

US08941412B2 Amplifiers using gated diodes 有权
标题翻译：放大器采用门控二极管
公开(公告)号：US08941412B2
公开(公告)日：2015-01-27
申请号：US13604995
申请日：2012-09-06
申请人： Wing K. Luk , Robert H. Dennard
发明人： Wing K. Luk , Robert H. Dennard
IPC分类号： H03F3/72 , G11C7/06 , H03F1/56 , H01L27/08 , H01L29/739
CPC分类号： H03F1/56 , G11C7/06 , H01L27/0811 , H01L29/7391 , H03F2200/183
摘要： A circuit comprises a control line and a two terminal semiconductor device having a first terminal is coupled to a signal line, and a second terminal coupled to the control line. The semiconductor device has a capacitance when a voltage on the first terminal is above a threshold and has a smaller capacitance when a voltage on the first terminal is below the threshold. A signal is placed on the signal line and a voltage on the control line is modified. When the signal falls below the threshold, the semiconductor device acts as a very small capacitor and the output will be a small value. When the signal is above the threshold, the semiconductor device acts as a large capacitor and the output will be influenced by the signal and the modified voltage on the control line and the signal is amplified.
摘要翻译：电路包括控制线和具有第一端子的两端子半导体器件耦合到信号线，以及耦合到控制线的第二端子。当第一端子上的电压高于阈值时，半导体器件具有电容，并且当第一端子上的电压低于阈值时具有较小的电容。信号被置于信号线上，控制线上的电压被改变。当信号低于阈值时，半导体器件充当非常小的电容器，并且输出将是小的值。当信号高于阈值时，半导体器件用作大电容器，输出将受到信号和控制线上修改的电压的影响，信号被放大。

3. 发明授权

US08552500B2 Structure for CMOS ETSOI with multiple threshold voltages and active well bias capability 有权
标题翻译：具有多个阈值电压和有源阱偏置能力的CMOS ETSOI的结构
公开(公告)号：US08552500B2
公开(公告)日：2013-10-08
申请号：US13114283
申请日：2011-05-24
申请人： Robert H. Dennard , Terence B. Hook
发明人： Robert H. Dennard , Terence B. Hook
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/823878 , H01L21/823892 , H01L21/84
摘要： A semiconductor substrate having a first type of conductivity and a top surface, a layer of oxide disposed over the top surface and a semiconductor layer disposed over the layer of oxide. A plurality of transistor devices are disposed upon the semiconductor layer. Each transistor device includes a channel between a source and a drain, where some transistor devices have a first type of channel conductivity and the remaining transistor devices have a second type of channel conductivity. A well region is formed adjacent to the top surface. The well region has a second type of conductivity. First trench isolation regions are between adjacent transistor devices that extend through the semiconductor layer. Second trench isolation regions are between adjacent transistor devices of opposite channel conductivity.
摘要翻译：具有第一导电类型和顶表面的半导体衬底，设置在顶表面上的氧化物层和设置在氧化物层上的半导体层。多个晶体管器件设置在半导体层上。每个晶体管器件包括在源极和漏极之间的沟道，其中一些晶体管器件具有第一类型的沟道导电性，并且剩余的晶体管器件具有第二类型的沟道导电性。阱区域邻近顶表面形成。阱区具有第二类导电性。第一沟槽隔离区域在延伸穿过半导体层的相邻晶体管器件之间。第二沟槽隔离区域在相反的沟道导电性的相邻晶体管器件之间。

4. 发明授权

US08531001B2 Complementary bipolar inverter 有权
标题翻译：互补双极型逆变器
公开(公告)号：US08531001B2
公开(公告)日：2013-09-10
申请号：US13158419
申请日：2011-06-12
申请人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L21/70
CPC分类号： H01L27/1203 , H01L21/8228 , H01L21/84 , H01L27/082
摘要： An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.
摘要翻译：示例性实施例是互补晶体管反相器电路。电路包括绝缘体上半导体（SOI）衬底，制造在SOI衬底上的横向PNP双极晶体管，以及制造在SOI衬底上的横向NPN双极晶体管。横向PNP双极晶体管包括PNP基极，PNP发射极和PNP集电极。横向NPN双极晶体管包括NPN基极，NPN发射极和NPN集电极。 PNP基极，PNP发射极，PNP集电极，NPN基极，NPN发射极和NPN集电极邻接SOI衬底的埋层绝缘体。

5. 发明授权

US08530287B2 ETSOI CMOS with back gates 有权
标题翻译：带后门的ETSOI CMOS
公开(公告)号：US08530287B2
公开(公告)日：2013-09-10
申请号：US13611656
申请日：2012-09-12
申请人： Jin Cai , Robert H Dennard , Ali Khakifirooz
发明人： Jin Cai , Robert H Dennard , Ali Khakifirooz
IPC分类号： H01L21/84
CPC分类号： H01L27/1203
摘要： A method to fabricate a structure includes providing a silicon-on-insulator wafer, implanting through a semiconductor layer and an insulating layer a functional region having a first type of conductivity to be adjacent to a top surface of the substrate; implanting within the functional region through the semiconductor layer and the insulating layer an electrically floating back gate region having a second type of conductivity; forming isolation regions in the semiconductor layer; forming first and second transistor devices to have the same type of conductivity over the semiconductor layer such that one of the transistor devices overlies the implanted back gate region and the other one of the transistor devices overlies only the underlying top surface of the functional region not overlapped by the implanted back gate region; and providing an electrical contact to the functional region for applying a bias voltage.
摘要翻译：制造结构的方法包括提供绝缘体上硅晶片，通过半导体层和绝缘层注入具有与衬底顶表面相邻的第一导电类型的功能区域; 在功能区域内通过半导体层和绝缘层注入具有第二类导电性的电浮置背栅区; 在半导体层中形成隔离区; 形成第一和第二晶体管器件以在半导体层上具有相同类型的导电性，使得晶体管器件中的一个覆盖在注入的背栅极区域上，另一个晶体管器件仅覆盖不重叠的功能区域的下面的顶部表面通过植入的背栅区; 以及向所述功能区域提供电接触以施加偏置电压。

6. 发明申请

US20120300544A1 GATED DIODE MEMORY CELLS 有权
标题翻译：闭合二极管记忆细胞
公开(公告)号：US20120300544A1
公开(公告)日：2012-11-29
申请号：US13571094
申请日：2012-08-09
申请人： Wing K. Luk , Robert H. Dennard
发明人： Wing K. Luk , Robert H. Dennard
IPC分类号： G11C11/36
CPC分类号： G11C11/36 , G11C11/404
摘要： A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).
摘要翻译：提供了门控二极管存储单元，其包括一个或多个晶体管，例如场效应晶体管（FET）以及与FET进行信号通信的门控二极管，使得门控二极管的栅极与源极第一FET，其中栅极二极管的栅极形成存储单元的一个端子，栅极二极管的源极形成存储单元的另一个端子，第一FET的漏极与位线（BL）信号通信，并且第一FET的栅极与写入字线（WLw）进行信号通信，门控二极管的源极与读取字线（WLr）进行信号通信。

7. 发明申请

US20120284541A1 POWER DELIVERY IN A HETEROGENEOUS 3-D STACKED APPARATUS 有权
标题翻译：在异质三维堆叠设备中的电力输送
公开(公告)号：US20120284541A1
公开(公告)日：2012-11-08
申请号：US13552091
申请日：2012-07-18
申请人： Robert H. Dennard , Eren Kursun
发明人： Robert H. Dennard , Eren Kursun
IPC分类号： G06F1/26
CPC分类号： H01L25/18 , H01L23/642 , H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , Y10T307/50
摘要： A heterogeneous three-dimensional (3-D) stacked apparatus is provided that includes multiple layers arranged in a stacked configuration with a lower layer configured to receive a board-level voltage and one or more upper layers stacked above the lower layer. The heterogeneous 3-D stacked apparatus also includes multiple tiles per layer, where each tile is designed to receive a separately regulated voltage. The heterogeneous 3-D stacked apparatus additionally includes at least one layer in the one or more upper layers with voltage converters providing the separately regulated voltage converted from the board-level voltage.
摘要翻译：提供了一种不均匀的三维（3-D）层叠装置，其包括以堆叠配置布置的多个层，其中下层被配置为接收板级电压，以及堆叠在下层上方的一个或多个上层。异质三维层叠装置还包括每层多个瓦片，其中每个瓦片被设计成接收单独调节的电压。异质三层堆叠装置还包括在一个或多个上层中的至少一个层，其中电压转换器提供从板级电压转换的单独调节的电压。

8. 发明申请

US20120112309A1 LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION 有权
标题翻译：具有后续自对准的双盒式背盖的低成本制造硅绝缘体波纹
公开(公告)号：US20120112309A1
公开(公告)日：2012-05-10
申请号：US13350889
申请日：2012-01-16
申请人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen Shi , Jeng-Bang Yau
发明人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L21/84 , H01L21/76254 , H01L21/76275 , H01L21/76283 , H01L27/1203
摘要： A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed.
摘要翻译：用于制造集成电路器件的半导体衬底结构包括块状衬底; 形成在所述本体基板上的下绝缘层，所述下绝缘层由一对具有接合界面的分离的绝缘层形成; 形成在下绝缘层上的导电层; 在所述导电层上形成具有蚀刻停止特性的绝缘体; 形成在所述蚀刻停止层上的上绝缘层; 以及形成在上绝缘层上的半导体层。还公开了一种随后构建双深度浅沟槽隔离的方案，其中在与这种半导体衬底中的有源区域中较浅的STI自对准的背栅层中的较深STI相比较。

9. 发明申请

US20100259299A1 VOLTAGE CONVERSION AND INTEGRATED CIRCUITS WITH STACKED VOLTAGE DOMAINS 有权
标题翻译：具有堆叠电压域的电压转换和集成电路
公开(公告)号：US20100259299A1
公开(公告)日：2010-10-14
申请号：US12422391
申请日：2009-04-13
申请人： Robert H. Dennard , Brian L. Ji
发明人： Robert H. Dennard , Brian L. Ji
IPC分类号： H03K19/0175
CPC分类号： H03K3/00 , H02M3/07 , H03K3/356139 , H03K19/01806 , H03K19/018521
摘要： An integrated circuit (IC) system includes a plurality of ICs configured in a stacked voltage domain arrangement such that a low side supply rail of at least one of ICs is common with a high side supply rail of at least another of the ICs; a reversible voltage converter coupled to power rails of each of the plurality of ICs, the reversible voltage converter configured for stabilizing individual voltage domains corresponding to each IC; and one or more data voltage level shifters configured to facilitate data communication between ICs operating in different voltage domains, wherein an input signal of a given logic state corresponding to one voltage in a first voltage domain is shifted to an output signal of the same logic state at another voltage in a second voltage domain.
摘要翻译：集成电路（IC）系统包括多个集成电路，其配置成堆叠的电压域布置，使得IC中的至少一个的低侧供电导轨与至少另一个IC的高侧供电导轨共同; 耦合到所述多个IC中的每一个的电源轨的可逆电压转换器，所述可逆电压转换器被配置用于稳定对应于每个IC的各个电压域; 以及一个或多个数据电压电平移位器，被配置为促进在不同电压域中操作的IC之间的数据通信，其中对应于第一电压域中的一个电压的给定逻辑状态的输入信号被转移到相同逻辑状态的输出信号在第二电压域中的另一电压。

10. 发明申请

US20100176453A1 LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH BUILT-IN SHALLOW TRENCH ISOLATION IN BACK GATE LAYER 失效
公开(公告)号：US20100176453A1
公开(公告)日：2010-07-15
申请号：US12352071
申请日：2009-01-12
申请人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen Shi , Jeng-Bang Yau
发明人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L29/78 , H01L23/58 , H01L21/30
CPC分类号： H01L21/84 , H01L21/76254 , H01L29/78648
摘要： A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed.

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