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1. 发明授权

US09164563B2 Processor noise mitigation using differential critical path monitoring 有权
标题翻译：使用差分关键路径监控的处理器噪声抑制
公开(公告)号：US09164563B2
公开(公告)日：2015-10-20
申请号：US13479797
申请日：2012-05-24
申请人： Robert W. Berry, Jr. , Michael S. Floyd , Jarom Pena , Ryan J. Pennington , Catherine Sherry
发明人： Robert W. Berry, Jr. , Michael S. Floyd , Jarom Pena , Ryan J. Pennington , Catherine Sherry
IPC分类号： G06F1/28 , G06F1/26 , G06F11/30
CPC分类号： G06F1/28 , G06F1/26 , G06F11/3062
摘要： An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.
摘要翻译：提供了一种处理器电源噪声抑制方法。在一个方面，该方法包括可操作地耦合到处理器以执行程序操作的中央计算单元。该方法还包括校准电路，其适于确定要用于通过使用检测电路动态执行的比较的处理器上的第一阈值。一种检测电路，适用于动态地监视处理器的系统操作并指示是否违反了第一阈值，还提供了一种适于在一个或多个电压感测测量违反第一阈值时防止电压下降的计数电路。

2. 发明申请

US20130103354A1 DETECTING CROSS-TALK ON PROCESSOR LINKS 有权
标题翻译：检测处理器链接的交叉口
公开(公告)号：US20130103354A1
公开(公告)日：2013-04-25
申请号：US13281097
申请日：2011-10-25
申请人： Robert W. Berry, JR. , Anand Haridass , Prasanna Jayaraman
发明人： Robert W. Berry, JR. , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F11/30
CPC分类号： G06F9/30145 , G06F9/30 , G06F11/3409 , G06F11/3414 , G06F11/3466 , G06F11/349
摘要： A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.
摘要翻译：多个处理器链路中的第一个处理器链路的多个数据通路中的第一个被确定为对于多个数据通道具有最弱的基本性能测量。经由剩余处理器链路的第一组发送切换数据模式，并且经由剩余处理器链路的第二组发送安静数据模式。如果第一数据线的性能相对于相应的基本性能测量增加，则剩余处理器链路的第一组从剩余处理器链路中消除。如果第一数据通道的性能相对于相应的基本性能测量值降低，则剩余处理器链路的第二组从剩余处理器链路中消除。重复执行上述操作，直到识别出被确定为降低多个数据通道中的第一个数据通道的性能的攻击者处理器链路。

3. 发明申请

US20080312863A1 SYSTEM AND METHOD FOR IMPLEMENTING A PROGRAMMABLE DMA MASTER WITH DATE CHECKING UTILIZING A DRONE SYSTEM CONTROLLER 失效
标题翻译：用于执行可编程DMA主机的系统和方法，日期检查使用DRONE系统控制器
公开(公告)号：US20080312863A1
公开(公告)日：2008-12-18
申请号：US12187199
申请日：2008-08-06
申请人： Robert W. Berry, JR. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
发明人： Robert W. Berry, JR. , Michael Criscolo , Christopher J. Kuruts , James P. Kuruts , Steven J. Smolski
IPC分类号： G11C29/00 , G06F19/00
CPC分类号： G11C29/48 , G06F11/26
摘要： A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.
摘要翻译：一种用于使用无人机系统控制器实现具有数据检查的可编程DMA主机的方法，系统和计算机可用介质。根据本发明的实施例，无人机处理器生成随机数据的集合，并将随机数据的集合的第一和第二副本存储在无人机存储器中的第一和第二存储器位置中。无人机处理器将随机数据集合的第三副本写入处理器存储器。当无人机处理器从处理器存储器检索第三副本时，无人机处理器将第三副本写入无人机存储器中的第二存储器位置。当无人机处理器将第一副本与第三副本进行比较时，将比较结果写入无人机处理器内的状态位置。

4. 发明授权

US5375091A Method and apparatus for memory dynamic burn-in and test 失效
标题翻译：用于记忆动态老化和测试的方法和装置
公开(公告)号：US5375091A
公开(公告)日：1994-12-20
申请号：US163803
申请日：1993-12-08
申请人： Robert W. Berry, Jr. , Bernd K. F. Koenemann , William J. Scarpero, Jr. , Philip G. Shephard, III , Kenneth D. Wagner , Gulsun Yasar
发明人： Robert W. Berry, Jr. , Bernd K. F. Koenemann , William J. Scarpero, Jr. , Philip G. Shephard, III , Kenneth D. Wagner , Gulsun Yasar
IPC分类号： G11C29/10 , G11C29/50 , G11C13/00
CPC分类号： G11C29/10 , G11C29/50
摘要： A memory embedded in a integrated processor chip is dynamically stressed tested by repeatedly writing a test pattern to the data locations of the memory in which a high percentage of the memory cells are sequentially written with complementary data in order to create a high stress on the memory devices. The test pattern is generated as a function of the number of address locations of the memory and the number of data bits of a memory data word. The test pattern is rotated each time the memory is addressed. The test pattern preferably has a contiguous group of digits with the number of digits in the contiguous group being a function of the number of address locations and the number of data bits in the memory word. The memory data input register is configured as a recirculating loop and additional dummy bits are added to provide recirculating loops longer than the data input register. A plurality of independent circulating loops may be created in the data input register or in combination with a number of dummy register bits.
摘要翻译：嵌入在集成处理器芯片中的存储器通过重复地将测试图案写入存储器的数据位置而被动态地受到压力测试，其中高百分比的存储器单元被顺序地写有补充数据，以便在存储器上产生高应力设备。作为存储器的地址位置的数量和存储器数据字的数据位的数量的函数产生测试图案。每次存储器寻址时，测试模式都会旋转。测试图案优选地具有连续的数字组，连续组中的位数是作为存储器字中的地址位置数和数据位数的函数。存储器数据输入寄存器被配置为循环回路，并添加额外的虚拟位以提供比数据输入寄存器更长的再循环回路。可以在数据输入寄存器中或与多个虚拟寄存器位组合地产生多个独立的循环回路。

5. 发明授权

US4179001A Underground drilling and casing method and apparatus 失效
标题翻译：地下钻井及套管方法及装置
公开(公告)号：US4179001A
公开(公告)日：1979-12-18
申请号：US836219
申请日：1977-09-23
申请人： Norman H. Still , Robert W. Berry, Jr.
发明人： Norman H. Still , Robert W. Berry, Jr.
IPC分类号： E21B7/20 , E21B17/10 , E21D3/00 , E21B19/00
CPC分类号： E21B17/10 , E21B7/20
摘要： In an underground mine, a machine for drilling upwardly is placed in one tunnel of the mine and is used to drill a vertical shaft communicating with another tunnel at a higher elevation. The machine is operated so as to install a liner or casing in the shaft in a step-by-step fashion, substantially concurrently with the corresponding steps of the drilling operation.
摘要翻译：在地下矿井中，向上钻孔的机器放置在矿井的一个隧道内，用于在较高高度与另一个隧道相通的垂直轴钻。操作该机器，以便以一步一步的方式将衬套或套管安装在轴中，基本上与钻孔操作的相应步骤同时进行。

6. 发明授权

US5278842A Delay test coverage enhancement for logic circuitry employing level sensitive scan design 失效
标题翻译：采用电平敏感扫描设计的逻辑电路的延迟测试覆盖增强
公开(公告)号：US5278842A
公开(公告)日：1994-01-11
申请号：US650387
申请日：1991-02-04
申请人： Robert W. Berry, Jr. , Jacob Savir
发明人： Robert W. Berry, Jr. , Jacob Savir
IPC分类号： G01R31/317 , G01R31/28 , G01R31/30 , G01R31/3185 , H04B17/00
CPC分类号： G01R31/31858 , G01R31/3016
摘要： By selectively associating output signal lines with logic circuit input signal lines, it is possible to produce a combination logic circuit and latch string in which no pair of adjacent latches is connected to the same cone of logic in the logic circuit. This provides greatly improved capabilities for delay or AC circuit test with respect to the independence of test pairs of excitation data. The objective may also be achieved in whole or in part through the use of dummy latch elements which do not feed any logic circuit input signal lines.
摘要翻译：通过选择性地将输出信号线与逻辑电路输入信号线相关联，可以产生组合逻辑电路和锁存串，其中没有一对相邻锁存器连接到逻辑电路中的同一逻辑锥。相对于激励数据的测试对的独立性，这为延迟或AC电路测试提供了极大的改进的能力。也可以通过使用不馈送任何逻辑电路输入信号线的虚拟锁存元件来全部或部分地实现该目的。

7. 发明授权

US4210406A Drill with replaceable inserts 失效
标题翻译：用可更换刀片钻
公开(公告)号：US4210406A
公开(公告)日：1980-07-01
申请号：US938765
申请日：1978-09-01
申请人： Robert W. Berry, Jr.
发明人： Robert W. Berry, Jr.
IPC分类号： B23B51/04 , B23B51/00
CPC分类号： B23B51/048 , Y10S408/713 , Y10T408/905
摘要： A drill body for drilling solid metal and for finish boring having, at the working end, two or more replaceable, indexable, hard metal inserts dimensioned and spaced radially to cut equal volumes of metal. The inserts are retained in pockets by a headed screw with a through passage for a wrench. The outside insert is also shaped and positioned so the drill body may be shifted radially from the drilling axis and used as a boring bar.
摘要翻译：用于钻出固体金属并用于精加工的钻体，其在工作端具有两个或更多个可更换的可转位的硬质金属插件，其尺寸和径向间隔开以切割等体积的金属。插入物通过带有用于扳手的通道的头部螺钉保持在口袋中。外部插入件也被成形和定位，使得钻体可以从钻孔轴线径向偏移并用作钻杆。

8. 发明申请

US20130318364A1 PROCESSOR NOISE MITIGATION USING DIFFERENTIAL CRITICAL PATH MONITORING 有权
标题翻译：使用差分关键路径监测的处理器噪声减轻
公开(公告)号：US20130318364A1
公开(公告)日：2013-11-28
申请号：US13479797
申请日：2012-05-24
申请人： Robert W. Berry, JR. , Michael S. Floyd , Jarom Pena , Ryan J. Pennington , Catherine Sherry
发明人： Robert W. Berry, JR. , Michael S. Floyd , Jarom Pena , Ryan J. Pennington , Catherine Sherry
IPC分类号： G06F1/26
CPC分类号： G06F1/28 , G06F1/26 , G06F11/3062
摘要： An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.
摘要翻译：提供了一种处理器电源噪声抑制方法。在一个方面，该方法包括可操作地耦合到处理器以执行程序操作的中央计算单元。该方法还包括校准电路，其适于确定要用于通过使用检测电路动态执行的比较的处理器上的第一阈值。一种检测电路，适用于动态地监视处理器的系统操作并指示是否违反了第一阈值，还提供了一种适于在一个或多个电压感测测量违反第一阈值时防止电压下降的计数电路。

9. 发明授权

US4189265A Positive chip control insert 失效
标题翻译：正芯片控制插入
公开(公告)号：US4189265A
公开(公告)日：1980-02-19
申请号：US942549
申请日：1978-09-15
申请人： Leonard R. Arnold , Robert W. Berry, Jr.
发明人： Leonard R. Arnold , Robert W. Berry, Jr.
IPC分类号： B23B27/14 , B26D1/12
CPC分类号： B23B27/143 , B23B2200/085 , B23B2200/204 , B23B2200/321 , Y10T407/235
摘要： An indexable, insert for single-point and multiple-point negative rake holding devices which convert the cutting point to a positive cutting geometry. The insert has straight descending and widening V-shaped grooves from each corner along the adjacent sides, each groove modulating into a low angle straight section which rises abruptly into a radial cross-ridge at the midpoint of the groove, the cross-ridge rising to a crest line below the plane of the resulting island created by the grooves around the insert.
摘要翻译：用于将切割点转换为正切削几何的单点和多点负耙保持装置的可转位插入件。插入件沿着相邻的侧面从每个拐角处具有直下降和变宽的V形凹槽，每个凹槽调制成一个低角度的直线段，其在槽的中点突然地上升到径向的交叉脊中，在由所述插入件周围的槽形成的所产生的岛的平面下方的波峰线。

10. 发明授权

US4083416A Collapsible cutterhead for drilling upward 失效
标题翻译：可折叠的刀头向上钻
公开(公告)号：US4083416A
公开(公告)日：1978-04-11
申请号：US787283
申请日：1977-04-13
申请人： Norman H. Still , Robert W. Berry, Jr.
发明人： Norman H. Still , Robert W. Berry, Jr.
IPC分类号： E21B7/20 , E21B10/34 , E21B10/66 , E21B9/00
CPC分类号： E21B10/34 , E21B10/66 , E21B7/20
摘要： A cutterhead adapted for drilling a hole upwardly in the earth, and to then be withdrawn downwardly through a casing which is inserted underneath the cutterhead, characterized by gauge cutters which are pivotally mounted on the cutterhead so that they will pivot upward and radially inward when the cutterhead is drawn into the casing, and also characterized by stabilizer rollers mounted on removable frames that can be detached.
摘要翻译：一种用于在地球上向上钻孔的刀头，然后通过插入刀架下方的壳体向下抽出，其特征在于，在刀盘上枢转地安装有量规切割器，使得当刀头向上和向内转动时刀头被拉入外壳，其特征还在于安装在可拆卸的可拆卸框架上的稳定辊。

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