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1. 发明授权

US08448006B2 Performing virtual and/or physical resource management for power management 失效
标题翻译：执行电源管理的虚拟和/或物理资源管理
公开(公告)号：US08448006B2
公开(公告)日：2013-05-21
申请号：US12907190
申请日：2010-10-19
申请人： Michael S. Floyd , Christopher Francois , Naresh Nayar , Karthick Rajamani , Freeman L. Rawson, III , Randal C. Swanberg , Malcolm S. Ware
发明人： Michael S. Floyd , Christopher Francois , Naresh Nayar , Karthick Rajamani , Freeman L. Rawson, III , Randal C. Swanberg , Malcolm S. Ware
IPC分类号： G06F1/32
CPC分类号： G06F9/5094 , G06F1/3206 , G06F1/3228 , G06F1/3287 , G06F1/329 , Y02D10/171 , Y02D10/22 , Y02D10/24
摘要： A mechanism is provided for directed resource folding for power management. The mechanism receives a set of static platform characteristics and a set of dynamic platform characteristics for a set of resources associated with the data processing system thereby forming characteristic information. The mechanism determines whether one or more conditions have been met for each resource in the set of resources using the characteristic information. Responsive to the one or more conditions being met, the mechanism performs a resource optimization to determine at least one of a first subset of resources in the set of resources to keep active and a second subset of resources in the set of resources to dynamically fold. Based on the resource optimization, the mechanism performs either a virtual resource optimization to optimally schedule the first subset of resources or a physical resource optimization to dynamically fold the second subset of resources.
摘要翻译：提供了一种用于电源管理的定向资源折叠的机制。该机制接收与数据处理系统相关联的一组资源的一组静态平台特性和一组动态平台特性，从而形成特征信息。该机制使用特征信息确定资源集合中的每个资源是否满足一个或多个条件。响应于满足的一个或多个条件，机制执行资源优化以确定资源集合中的资源的第一子集中的至少一个以保持活动，并且该资源集合中的资源的第二子集动态地折叠。基于资源优化，该机制执行虚拟资源优化以优化调度资源的第一子集或物理资源优化以动态地折叠资源的第二子集。

2. 发明申请

US20130055185A1 VERTICAL POWER BUDGETING AND SHIFTING FOR 3D INTEGRATION 有权
标题翻译：用于3D集成的垂直功率投影和移位
公开(公告)号：US20130055185A1
公开(公告)日：2013-02-28
申请号：US13217429
申请日：2011-08-25
申请人： PRADIP BOSE , GARY D. CARPENTER , MICHAEL S. FLOYD , EREN KURSUN , PHILLIP J. RESTLE , MICHAEL R. SCHEUERMANN
发明人： PRADIP BOSE , GARY D. CARPENTER , MICHAEL S. FLOYD , EREN KURSUN , PHILLIP J. RESTLE , MICHAEL R. SCHEUERMANN
IPC分类号： G06F17/50
CPC分类号： H01L23/50 , G06F17/5045 , G06F2217/78 , H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565
摘要： A method is provided for managing power distribution on a 3D chip stack having two or more strata, a plurality of vertical power delivery structures, and multiple stack components. At least two stack components are on different strata. Operating modes are stored that respectively have different power dissipations. A respective effective power budget is determined for each of the at least two stack components based on respective ones of the operating modes targeted therefor, and power characteristics and thermal characteristics of at least some of the stack components inclusive or exclusive of the at least two stack components. The respective ones of the plurality of operating modes targeted for the at least two stack components are selectively accepted or re-allocated based on the respective effective power budget for each of the at least two stack components, power constraints, and thermal constraints. The power constraints include vertical structure electrical constraints.
摘要翻译：提供了一种用于管理具有两个或更多个层，多个垂直功率传递结构和多个堆栈组件的3D芯片堆叠上的功率分配的方法。至少两个堆叠组件位于不同的层。存储分别具有不同功耗的工作模式。基于针对其的各个操作模式确定所述至少两个堆叠组件中的每一个的相应的有效功率预算，以及包括或排除所述至少两个堆叠的至少一些堆叠组件的功率特性和热特性组件。基于用于至少两个堆叠组件中的每一个，功率约束和热约束的相应的有效功率预算来选择性地接受或重新分配针对至少两个堆叠组件的多个操作模式中的各个操作模式。功率约束包括垂直结构电气约束。

3. 发明授权

US08122312B2 Internally controlling and enhancing logic built-in self test in a multiple core microprocessor 失效
标题翻译：在多核微处理器中内部控制和增强逻辑内置自检
公开(公告)号：US08122312B2
公开(公告)日：2012-02-21
申请号：US12423442
申请日：2009-04-14
申请人： Michael S. Floyd , Joshua D. Friedrich , Robert B. Gass , Norman K. James
发明人： Michael S. Floyd , Joshua D. Friedrich , Robert B. Gass , Norman K. James
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/31724 , G06F11/27
摘要： A mechanism is provided for internally controlling and enhancing logic built-in self test in a multiple core microprocessor. The control core may use architectural support for scan and external scan communication (XSCOM) to independently test the other cores while adjusting their frequency and/or voltage. A program loaded onto the control core may adjust the frequency and configure the LBIST to run on each of the cores under test. Once LBIST has completed on a core under test, the control core's program may evaluate the results and decide a next test to run for that core. For isolating failing latch positions, the control core may iteratively configure the LBIST mask and sequence registers on the core under test to determine the location of the failing latch. The control core may control the LBIST stump masks to isolate the failure to a particular latch scan ring and then position within that ring.
摘要翻译：提供了一种用于在多核微处理器内部控制和增强逻辑内置自检的机制。控制核心可以使用架构支持扫描和外部扫描通信（XSCOM）来独立测试其他内核，同时调整其频率和/或电压。加载到控制核心上的程序可以调整频率并配置LBIST以在被测试的每个核心上运行。一旦LBIST已经在被测核心上完成，控制核心的程序可以评估结果并决定下一个测试以运行该核心。为了隔离失效的锁存位置，控制核可以迭代地配置待测核心上的LBIST掩码和序列寄存器，以确定故障锁存器的位置。控制核心可以控制LBIST残端掩模以将故障隔离到特定的锁存扫描环，然后位于该环内。

4. 发明申请

US20120005513A1 PERFORMANCE CONTROL OF FREQUENCY-ADAPTING PROCESSORS BY VOLTAGE DOMAIN ADJUSTMENT 有权
标题翻译：通过电压调整对频率适配处理器进行性能控制
公开(公告)号：US20120005513A1
公开(公告)日：2012-01-05
申请号：US12827432
申请日：2010-06-30
申请人： Bishop C. Brock , John B. Carter , Alan J. Drake , Michael S. Floyd , Charles R. Lefurgy , Malcolm S. Ware
发明人： Bishop C. Brock , John B. Carter , Alan J. Drake , Michael S. Floyd , Charles R. Lefurgy , Malcolm S. Ware
IPC分类号： G06F1/26 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A performance control technique for a processing system that includes one or more adaptively-clocked processor cores provides improved performance/power characteristics. An outer feedback loop adjusts the power supply voltage(s) provided to the power supply voltage domain(s) powering the core(s), which may be on a per-core basis or include multiple cores per voltage domain. The outer feedback loop operates to ensure that each core is meeting specified performance, while the cores also include an inner feedback loop that adjusts their processor clock or other performance control mechanism to maximize performance under present operating conditions and within a margin of safety. The performance of each core is measured and compared to a target performance. If the target performance is not met for each core in a voltage domain, the voltage is raised for the voltage domain until all cores meet the target performance.
摘要翻译：包括一个或多个自适应时钟的处理器核心的处理系统的性能控制技术提供了改进的性能/功率特性。外部反馈环路调整提供给供电核心的电源电压域的电源电压（其可以是基于每个核心的或者每个电压域包括多个核心）。外部反馈环路用于确保每个核心满足指定的性能，而核心还包括一个内部反馈回路，调整其处理器时钟或其他性能控制机制，以最大限度地提高现有操作条件下的性能并在安全范围之内。测量每个核心的性能并将其与目标性能进行比较。如果电压域中的每个核心的目标性能不能满足，则电压域的电压将升高，直到所有核心满足目标性能。

5. 发明申请

US20090099817A1 Sensor Subset Selection for Reduced Bandwidth and Computation Requirements 失效
标题翻译：传感器子集选择降低带宽和计算要求
公开(公告)号：US20090099817A1
公开(公告)日：2009-04-16
申请号：US12342054
申请日：2008-12-22
申请人： Andreas Bieswanger , Michael S. Floyd , Andrew J. Geissler , Soraya Ghiasi , Hye-Young McCreary , Guillermo J. Silva , Malcolm S. Ware
发明人： Andreas Bieswanger , Michael S. Floyd , Andrew J. Geissler , Soraya Ghiasi , Hye-Young McCreary , Guillermo J. Silva , Malcolm S. Ware
IPC分类号： G06F11/30
CPC分类号： G06F11/30
摘要： A system for identifying a subset of sensors to sample to reduce the frequency of sensor access. The system determines rise times and records values for the sensors in the system. A time criticality of the sensors is determined based on the rise times. The system processes the sensors by first creating sensor subsets based on one or more constraints on the sensors. The system monitors the values of the sensors in a sensor subset and flags a sensor when it makes a determination that, prior to a next scheduled sampling of the sensor subset, the value of a sensor in the monitored sensor subset will exceed a threshold constraint. The system moves those flagged sensors to a second sensor subset which complies with the sensor's constraints.
摘要翻译：用于识别要采样的传感器子集以减少传感器访问频率的系统。系统确定系统中传感器的上升时间和记录值。基于上升时间确定传感器的时间关键度。该系统通过首先基于传感器上的一个或多个约束创建传感器子集来处理传感器。系统监测传感器子集中的传感器的值，并且当传感器确定在传感器子集的下次调度采样之前，所述传感器子集中的传感器的值将超过阈值约束时，对传感器进行标记。系统将标记的传感器移动到符合传感器约束的第二个传感器子集。

6. 发明申请

US20080133180A1 WEIGHTED EVENT COUNTING SYSTEM AND METHOD FOR PROCESSOR PERFORMANCE MEASUREMENTS 有权
标题翻译：加权事件计数系统和处理器性能测量方法
公开(公告)号：US20080133180A1
公开(公告)日：2008-06-05
申请号：US11951310
申请日：2007-12-05
申请人： Michael S. Floyd , Soraya Ghiasi , Thomas W. Keller , Karthick Rajamani , Freeman Leigh Rawson , Juan C. Rubio
发明人： Michael S. Floyd , Soraya Ghiasi , Thomas W. Keller , Karthick Rajamani , Freeman Leigh Rawson , Juan C. Rubio
IPC分类号： G06F11/34
CPC分类号： G06F11/3466 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.
摘要翻译：用于处理器性能测量的加权事件计数系统和方法提供低延迟和低误差性能测量能力。加权性能计数器根据从处理器中的功能单元提供的多个事件信号累加性能计数。根据具有处理器性能的每个事件之间的相关性，将不同的权重应用于事件信号。权重可以由可编程寄存器提供，从而可以在程序控制下调整权重。事件信号可以被组合以减少事件信号集合的位宽，其中在组合结果的单个字段中合并相互排斥的事件和具有根据子总计合并的相同权重的事件。权重应用于组合结果，用于更新性能计数。电源管理软件或硬件可以使用性能计数来对处理器的运行参数进行调整。

7. 发明授权

US08943341B2 Minimizing power consumption for fixed-frequency processing unit operation 有权
标题翻译：降低固定频率处理单元运行的功耗
公开(公告)号：US08943341B2
公开(公告)日：2015-01-27
申请号：US13443301
申请日：2012-04-10
申请人： Malcolm S. Allen-Ware , Alan J. Drake , Wei Huang , Michael S. Floyd , Huajun Wen
发明人： Malcolm S. Allen-Ware , Alan J. Drake , Wei Huang , Michael S. Floyd , Huajun Wen
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172
摘要： A mechanism is provided for minimizing power consumption for operation of a fixed-frequency processing unit. A number of timeslots are counted in a time window where throttling is engaged to the fixed-frequency processing unit. The number of timeslots where throttling is engaged is divided by a total number of timeslots within the time window, thereby producing a performance loss (PLOSS) value. A determination is made as to whether determining whether the (PLOSS) value associated with the fixed-frequency processing unit is greater than an allowed performance loss (APLOSS) value. Responsive to the PLOSS value being less than or equal to the APLOSS value, a decrease in voltage supplied to the fixed-frequency processing unit is initiated.
摘要翻译：提供了一种用于最小化固定频率处理单元的操作的功耗的机构。在与固定频率处理单元接合节流的时间窗中计数多个时隙。将节流作业的时间间隔除以时间窗口内的总时间数，从而产生性能损失（PLOSS）值。确定确定与固定频率处理单元相关联的（PLOSS）值是否大于允许的性能损失（APLOSS）值。响应于PLOSS值小于或等于APLOSS值，开始向固定频率处理单元提供的电压的降低。

8. 发明授权

US08645640B2 Method and apparatus for supporting memory usage throttling 失效
标题翻译：支持内存使用限制的方法和装置
公开(公告)号：US08645640B2
公开(公告)日：2014-02-04
申请号：US13166054
申请日：2011-06-22
申请人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
发明人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
IPC分类号： G06F12/00
CPC分类号： G06Q50/10
摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.
摘要翻译：公开了一种用于在具有多个小灯的数据处理系统内提供系统存储器使用限制的装置。该装置包括系统存储器，存储器访问收集模块，存储器信用计费模块和存储器调节计数器。存储器访问收集模块从小数点内的第一高速缓冲存储器接收来自第一高速缓冲存储器的第一组信号和来自第二高速缓冲存储器的第二组信号。存储器信用计费模块根据从小巧的第一和第二高速缓存存储器的第一和第二组信号中提取的高速缓存访问的结果来跟踪每用户虚拟分区上的系统存储器的使用情况。存储器油门计数器用于提供节气门控制信号，以防止当系统存储器使用量超过预定值时对系统存储器的访问。

9. 发明授权

US08566618B2 Reliable setting of voltage and frequency in a microprocessor 有权
标题翻译：微处理器中电压和频率的可靠设置
公开(公告)号：US08566618B2
公开(公告)日：2013-10-22
申请号：US12573284
申请日：2009-10-05
申请人： Michael S. Floyd , Karthick Rajamani , Juan C. Rubio , Malcolm S. Ware
发明人： Michael S. Floyd , Karthick Rajamani , Juan C. Rubio , Malcolm S. Ware
IPC分类号： G06F1/00 , G06F1/26
CPC分类号： G06F1/3296 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/172
摘要： Managing operations associated with one or more voltage changes and one or more frequency changes. A voltage change request and a frequency change request are associated with dynamic voltage and frequency scaling (DVFS) operations. The DVFS operations are transmitted by the processors to be executed by one or more direct current assemblies. A sequence associated with the one or more voltage changes and a sequence associated with the one or more frequency changes are detected by the system. The sequences are dynamically modified to enable insertion of an additional voltage change, whereby the additional voltage change indicates completion of one or more previous voltage change requests. Completion of the voltage change request enables one or more subsequent voltage change requests to be processed. When a voltage change request is not successfully completed one or more future voltage changes are suspended.
摘要翻译：管理与一个或多个电压变化和一个或多个频率变化相关联的操作。电压变化请求和频率变化请求与动态电压和频率缩放（DVFS）操作相关联。 DVFS操作由处理器发送以由一个或多个直流组件执行。与该一个或多个电压变化相关联的序列和与一个或多个频率变化相关联的序列由系统检测。这些序列被动态地修改以允许插入额外的电压变化，由此额外的电压变化指示完成一个或多个先前的电压变化请求。完成电压变化请求使得能够处理一个或多个后续电压变化请求。当电压变化请求未成功完成时，一个或多个未来的电压变化被暂停。

10. 发明申请

US20120043982A1 CRITICAL PATH MONITOR HAVING SELECTABLE OPERATING MODES AND SINGLE EDGE DETECTION 有权
标题翻译：具有选择性操作模式和单边缘检测的关键路径监视器
公开(公告)号：US20120043982A1
公开(公告)日：2012-02-23
申请号：US12861289
申请日：2010-08-23
申请人： Gary D. Carpenter , Alan J. Drake , Michael S. Floyd , Robert M. Senger
发明人： Gary D. Carpenter , Alan J. Drake , Michael S. Floyd , Robert M. Senger
IPC分类号： G01R31/3187
CPC分类号： G01R31/31725
摘要： A critical path monitor having selectable data output modes provides additional information about critical path delay variation. A pulse is propagated through a synthesized path representing a critical path in a functional logic circuit and a synthesized path delay is measured by a monitoring circuit that detects the arrival of an edge of the pulse at the output of the synthesized delay. The measured delay is provided as a real-time output and a processed result of the measured delay is processed according to a data output mode selected from multiple selectable output modes, thereby providing different information describing the real-time data about critical path delay, such as a range of edge positions corresponding to a variation of the critical path delay.
摘要翻译：具有可选数据输出模式的关键路径监视器提供关于关键路径延迟变化的附加信息。脉冲通过表示功能逻辑电路中的关键路径的合成路径传播，合成路径延迟由检测脉冲边缘在合成延迟的输出处的监控电路测量。测量的延迟被提供为实时输出，并且根据从多个可选输出模式中选择的数据输出模式来处理测量的延迟的处理结果，从而提供描述关于关键路径延迟的实时数据的不同信息，例如作为对应于关键路径延迟的变化的边缘位置的范围。

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