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1. 发明授权

US08077814B2 Preamble acquisition without second order timing loops 有权
标题翻译：前导采集无二阶定时循环
公开(公告)号：US08077814B2
公开(公告)日：2011-12-13
申请号：US12960043
申请日：2010-12-03
申请人： Haitao Xia , Shih-Ming Shih , Ryan Yu , Marcus Marrow , Kai Keung Chan
发明人： Haitao Xia , Shih-Ming Shih , Ryan Yu , Marcus Marrow , Kai Keung Chan
IPC分类号： H04L27/06
CPC分类号： H04L7/08
摘要： A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop.
摘要翻译：通过获得与数据分组的前导部分相关联的第一多个样本和第二多个样本来调整时钟。使用时钟对第一多个采样和第二多个采样进行采样。至少部分地基于第一多个样本确定第一中间值，并且至少部分地基于第二多个样本来确定第二中间值。至少部分地基于第一中间值和第二中间值来确定与前导码部分的结尾相关联的结束值。时钟至少部分地基于结束值进行调整，而不使用二阶定时循环。

2. 发明授权

US08320512B2 Preamble acquisition without second order timing loops 有权
标题翻译：前导采集无二阶定时循环
公开(公告)号：US08320512B2
公开(公告)日：2012-11-27
申请号：US13291024
申请日：2011-11-07
申请人： Haitao Xia , Shih-Ming Shih , Ryan Yu , Marcus Marrow , Kai Keung Chan
发明人： Haitao Xia , Shih-Ming Shih , Ryan Yu , Marcus Marrow , Kai Keung Chan
IPC分类号： H04L7/00
CPC分类号： H04L7/08
摘要： A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop.
摘要翻译：通过获得与数据分组的前导部分相关联的第一多个样本和第二多个样本来调整时钟。使用时钟对第一多个采样和第二多个采样进行采样。至少部分地基于第一多个样本确定第一中间值，并且至少部分地基于第二多个样本来确定第二中间值。至少部分地基于第一中间值和第二中间值来确定与前导码部分的结尾相关联的结束值。时钟至少部分地基于结束值进行调整，而不使用二阶定时循环。

3. 发明申请

US20120117414A1 PREAMBLE ACQUISITION WITHOUT SECOND ORDER TIMING LOOPS 有权
标题翻译：前瞻性收购，没有第二个订单时机
公开(公告)号：US20120117414A1
公开(公告)日：2012-05-10
申请号：US13291024
申请日：2011-11-07
申请人： Haitao Xia , Shih-Ming Shih , Ryan Yu , Marcus Marrow , Kai Keung Chan
发明人： Haitao Xia , Shih-Ming Shih , Ryan Yu , Marcus Marrow , Kai Keung Chan
IPC分类号： G06F1/08
CPC分类号： H04L7/08
摘要： A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop.
摘要翻译：通过获得与数据分组的前导部分相关联的第一多个样本和第二多个样本来调整时钟。使用时钟对第一多个采样和第二多个采样进行采样。至少部分地基于第一多个样本确定第一中间值，并且至少部分地基于第二多个样本来确定第二中间值。至少部分地基于第一中间值和第二中间值来确定与前导码部分的结尾相关联的结束值。时钟至少部分地基于结束值进行调整，而不使用二阶定时循环。

4. 发明授权

US07460623B1 Digital two-stage automatic gain control 失效
标题翻译：数字两级自动增益控制
公开(公告)号：US07460623B1
公开(公告)日：2008-12-02
申请号：US10360834
申请日：2003-02-06
申请人： Vladimir Radionov , Ryan Yu
发明人： Vladimir Radionov , Ryan Yu
IPC分类号： H04L27/08
CPC分类号： H03G3/3089 , H03G2201/202 , H03G2201/302
摘要： A digital automatic gain control circuit is disclosed. The circuit includes a selector, a scaler, a detector, a gain adjustor and a controller. In one exemplary aspect, the selector receives an input signal having two components, namely, the in-phase (I) and quadrature (Q) components, in digital form. The selector then selects a subset of bits from each component based on a control signal provided by the controller. The two subsets are then forwarded to the scaler. The scaler then multiplies the two subsets respectively against a gain value to generate two multiplication results. A portion of each multiplication result is then provided as output by the scaler. The gain value and the subset selection are periodically adjusted in response to the scaler output. The adjustments with respect to the gain value and the subset selection are effectuated collectively by the detector, the gain adjustor and the controller.
摘要翻译：公开了一种数字自动增益控制电路。该电路包括选择器，定标器，检测器，增益调节器和控制器。在一个示例性方面，选择器以数字形式接收具有两个分量的输入信号，即同相（I）和正交（Q）分量。然后，选择器基于由控制器提供的控制信号从每个分量中选择一个比特的子集。然后将两个子集转发到缩放器。缩放器然后将两个子集分别乘以增益值以生成两个相乘结果。然后将每个乘法结果的一部分作为缩放器的输出提供。响应于缩放器输出周期性地调整增益值和子集选择。相对于增益值和子集选择的调整由检测器，增益调节器和控制器共同实现。

5. 发明授权

US07869547B1 Preamble acquisition without second order timing loops 有权
标题翻译：前导采集无二阶定时循环
公开(公告)号：US07869547B1
公开(公告)日：2011-01-11
申请号：US11784195
申请日：2007-04-04
申请人： Haitao Xia , Shih-Ming Shih , Ryan Yu , Marcus Marrow , Kai Keung Chan
发明人： Haitao Xia , Shih-Ming Shih , Ryan Yu , Marcus Marrow , Kai Keung Chan
IPC分类号： H04L27/06
CPC分类号： H04L7/08
摘要： Timing acquisition is performed. A first portion of a preamble having an end is sampled. A first phase value is determined based on the sampled first portion. A second portion of the preamble is sampled and a second phase value is determined based on the sampled second portion. An end phase value is extrapolated based at least in part the first phase value and the second phase value. A clock is adjusted using the extrapolated end phase value.
摘要翻译：执行定时采集。对具有结束的前同步码的第一部分进行采样。基于采样的第一部分确定第一相位值。对前导码的第二部分进行采样，并且基于采样的第二部分来确定第二相位值。至少部分地基于第一相位值和第二相位值来推定结束相位值。使用外插结束相位值调整时钟。

6. 发明申请

US20110075779A1 PREAMBLE ACQUISITION WITHOUT SECOND ORDER TIMING LOOPS 有权
标题翻译：前瞻性收购，没有第二个订单时机
公开(公告)号：US20110075779A1
公开(公告)日：2011-03-31
申请号：US12960043
申请日：2010-12-03
申请人： Haitao Xia , Shih-Ming Shih , Ryan Yu , Marcus Marrow , Kai Keung Chan
发明人： Haitao Xia , Shih-Ming Shih , Ryan Yu , Marcus Marrow , Kai Keung Chan
IPC分类号： H04L7/00
CPC分类号： H04L7/08
摘要： A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop.
摘要翻译：通过获得与数据分组的前导部分相关联的第一多个样本和第二多个样本来调整时钟。使用时钟对第一多个采样和第二多个采样进行采样。至少部分地基于第一多个样本确定第一中间值，并且至少部分地基于第二多个样本来确定第二中间值。至少部分地基于第一中间值和第二中间值来确定与前导码部分的结尾相关联的结束值。时钟至少部分地基于结束值进行调整，而不使用二阶定时循环。

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