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1. 发明申请

US20170365708A1 TRENCH POWER SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20170365708A1
公开(公告)日：2017-12-21
申请号：US15186685
申请日：2016-06-20
申请人： SINOPOWER SEMICONDUCTOR, INC.
发明人： PO-HSIEN LI , WEI-CHIEH LIN , JIA-FU LIN , GUO-LIANG YANG
IPC分类号： H01L29/78 , H01L29/66 , H01L29/10 , H01L29/06 , H01L29/40
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A trench power semiconductor device is provided. A trench gate structure of the trench power semiconductor device located in a cell trench of an epitaxial layer includes a first dielectric layer, a second dielectric layer, a gate electrode, a third dielectric layer, and a shielding layer. The second dielectric layer is interposed between the first and third dielectric layers, and the second dielectric layer is made from different material than the first dielectric layer. After performing a selective etching step on the second dielectric layer, a recess can be formed among the first, second and third dielectric layers. The gate electrode includes a conductive layer formed in the recess region, and the shielding electrode is surrounded by the third dielectric layer and insulated from the conductive layer.

2. 发明申请

US20170200822A1 DOUBLE GATE TRENCH POWER TRANSISTOR AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20170200822A1
公开(公告)日：2017-07-13
申请号：US14994250
申请日：2016-01-13
申请人： SINOPOWER SEMICONDUCTOR, INC.
发明人： PO-HSIEN LI , JIA-FU LIN , CHIA-CHENG CHEN , WEI-CHIEH LIN
IPC分类号： H01L29/78 , H01L29/10 , H01L29/66 , H01L29/40
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/513 , H01L29/66484 , H01L29/66734 , H01L29/7811 , H01L29/7831
摘要： A double gate trench power transistor and manufacturing method thereof are provided. The double gate trench power transistor gate structure includes an epitaxial layer, a trench structure formed in the epitaxial layer, at least two gate structures, and a shielding electrode structure. The trench structure includes a deep trench portion and two shallow trench portions respectively adjacent to two opposite sides of the deep trench portion. Each of the gate structures formed in each of the shallow trench portions includes a gate insulating layer and a gate electrode. The gate insulating layer has a first dielectric layer, a second dielectric layer and a third dielectric layer. The second dielectric layer is interposed between the first and third dielectric layers. Additionally, a portion of the gate insulating layer is in contact with a shielding dielectric layer of the shielding electrode structure.

3. 发明申请

US20160149034A1 POWER SEMICONDUCTOR DEVICE HAVING LOW ON-STATE RESISTANCE 有权
标题翻译：功率半导体器件具有低的状态电阻
公开(公告)号：US20160149034A1
公开(公告)日：2016-05-26
申请号：US14555518
申请日：2014-11-26
申请人： SINOPOWER SEMICONDUCTOR, INC.
发明人： PO-HSIEN LI , GUO-LIANG YANG
IPC分类号： H01L29/78 , H01L29/06 , H01L29/417 , H01L29/40 , H01L29/423
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/1095 , H01L29/407 , H01L29/7397 , H01L29/7811
摘要： A power semiconductor device having low on-state resistance includes a substrate having an epitaxial layer formed thereon, a gate structure, a termination structure, and a patterned conductive layer. The epitaxial layer has at least a first trench and a second trench. The gate structure is embedded in the first trench, including a gate electrode and a shielding electrode disposed under the gate electrode. The termination structure is embedded in the second trench, including a termination electrode. The patterned conductive layer is disposed above the epitaxial layer. Specially, the shield electrode of the gate structure and the termination electrode of the termination structure are configured to receive the gate voltage. The patterned conductive layer is configured to electrically contact said gate electrode and termination electrodes by a first contact plug and a second contact plug respectively.
摘要翻译：具有低导通电阻的功率半导体器件包括其上形成有外延层的衬底，栅极结构，端接结构和图案化导电层。外延层具有至少第一沟槽和第二沟槽。栅极结构嵌入在第一沟槽中，包括设置在栅电极下方的栅电极和屏蔽电极。端接结构嵌入在第二沟槽中，包括端接电极。图案化的导电层设置在外延层的上方。特别地，栅极结构的屏蔽电极和终端结构的终端电极被配置为接收栅极电压。图案化导电层被配置为分别通过第一接触插塞和第二接触插塞电接触所述栅电极和端接电极。

4. 发明申请

US20170213906A1 TRENCH POWER TRANSISTOR 有权
公开(公告)号：US20170213906A1
公开(公告)日：2017-07-27
申请号：US15005130
申请日：2016-01-25
申请人： SINOPOWER SEMICONDUCTOR, INC.
发明人： PO-HSIEN LI , GUO-LIANG YANG , JIA-FU LIN , WEI-CHIEH LIN
IPC分类号： H01L29/78 , H01L29/40 , H01L23/31 , H01L29/08 , H01L23/29 , H01L29/423 , H01L29/10
CPC分类号： H01L29/7813 , H01L23/291 , H01L23/3171 , H01L23/3178 , H01L23/3192 , H01L29/0619 , H01L29/0865 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A trench power transistor is provided. The trench gate structure of the trench power transistor includes at least one insulting layer, a gate electrode, and a shielding electrode, which are disposed in a trench of an epitaxial layer. The insulating layer formed on an inner wall of the active trench to isolate an epitaxial layer from the gate and the shielding electrodes. The insulating layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer. The first and second dielectric layers extend from an upper portion of the inner wall to a lower portion of the inner wall of the active trench. The third dielectric layer is formed on the second dielectric layer and located at the lower portion of the active trench. A portion of the second dielectric layer is interposed between the first and third dielectric layers.

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