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1. 发明授权

US08815697B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08815697B2
公开(公告)日：2014-08-26
申请号：US13478450
申请日：2012-05-23
申请人： Jun-Ho Yoon , Bong-Jin Kuh , Ki-Chul Kim , Gyung-Jin Min , Tae-Jin Park , Sang-Ryol Yang , Jung-Min Oh , Sang-Yoon Woo , Young-Sub Yoo , Ji-Eun Lee , Jong-Sung Lim , Yong-Moon Jang , Han-Mei Choi , Je-Woo Han
发明人： Jun-Ho Yoon , Bong-Jin Kuh , Ki-Chul Kim , Gyung-Jin Min , Tae-Jin Park , Sang-Ryol Yang , Jung-Min Oh , Sang-Yoon Woo , Young-Sub Yoo , Ji-Eun Lee , Jong-Sung Lim , Yong-Moon Jang , Han-Mei Choi , Je-Woo Han
IPC分类号： H01L21/3213 , H01L27/108 , H01L21/285
CPC分类号： H01L28/90 , H01L27/10852
摘要： Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.
摘要翻译：提供一种制造具有电容器的半导体器件的方法。该方法包括形成复合层，包括顺序地堆叠在第一至第n牺牲层和第一至第n支撑层上的交替层上的衬底上。形成贯穿复合层的多个开口。在多个开口中形成下电极。去除第一至第n牺牲层的至少部分以限定在多个开口中相邻的开口和形成在其中的下电极之间延伸的下电极的支撑结构，支撑结构包括第一至第n支撑层和间隙在第一至第n个支撑层中相邻的第一至第n个牺牲层已被去除之间的区域。在下电极上形成介电层，在电介质层上形成上电极。

2. 发明申请

US20130005110A1 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130005110A1
公开(公告)日：2013-01-03
申请号：US13478450
申请日：2012-05-23
申请人： Jun-Ho Yoon , Bong-Jin Kuh , Ki-Chul Kim , Gyung-Jin Min , Tae-Jin Park , Sang-Ryol Yang , Jung-Min Oh , Sang-Yoon Woo , Young-Sub Yoo , Ji-Eun Lee , Jong-Sung Lim , Yong-Moon Jang , Han-Mei Choi , Je-Woo Han
发明人： Jun-Ho Yoon , Bong-Jin Kuh , Ki-Chul Kim , Gyung-Jin Min , Tae-Jin Park , Sang-Ryol Yang , Jung-Min Oh , Sang-Yoon Woo , Young-Sub Yoo , Ji-Eun Lee , Jong-Sung Lim , Yong-Moon Jang , Han-Mei Choi , Je-Woo Han
IPC分类号： H01L21/02
CPC分类号： H01L28/90 , H01L27/10852
摘要： Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.
摘要翻译：提供一种制造具有电容器的半导体器件的方法。该方法包括形成复合层，包括顺序地堆叠在第一至第n牺牲层和第一至第n支撑层上的交替层上的衬底上。形成贯穿复合层的多个开口。在多个开口中形成下电极。去除第一至第n牺牲层的至少部分以限定在多个开口中相邻的开口和形成在其中的下电极之间延伸的下电极的支撑结构，支撑结构包括第一至第n支撑层和间隙在第一至第n个支撑层中相邻的第一至第n个牺牲层已被去除之间的区域。在下电极上形成介电层，在电介质层上形成上电极。

3. 发明申请

US20120115293A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120115293A1
公开(公告)日：2012-05-10
申请号：US13287509
申请日：2011-11-02
申请人： Jin-Tae NOH , Hun-Hyeong Lim , Ki-Hyun Hwang , Jin-Gyun Kim , Sang-Ryol Yang
发明人： Jin-Tae NOH , Hun-Hyeong Lim , Ki-Hyun Hwang , Jin-Gyun Kim , Sang-Ryol Yang
IPC分类号： H01L21/336 , H01L21/8234 , B82Y40/00
CPC分类号： H01L27/1157 , H01L27/10855 , H01L27/11582
摘要： In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.
摘要翻译：在制造半导体器件的方法中，多个牺牲层和多个绝缘中间层在衬底上重复交替。绝缘夹层包括与牺牲层的材料不同的材料。通过绝缘夹层和牺牲层形成至少一个开口。至少一个开口露出基板。种子层使用第一硅源气体形成在至少一个开口的内壁上。通过种植种子层在至少一个开口中形成多晶硅沟道。去除牺牲层以在绝缘夹层之间形成多个凹槽。在槽中分别形成有多个栅极结构。

4. 发明授权

US07510935B2 Method of manufacturing a charge-trapping dielectric and method of manufacturing a sonos-type non-volatile semiconductor device 有权
标题翻译：电荷俘获电介质的制造方法和声波型非易失性半导体器件的制造方法
公开(公告)号：US07510935B2
公开(公告)日：2009-03-31
申请号：US11468944
申请日：2006-08-31
申请人： Sung-Hae Lee , Ju-Wan Lim , Jae-Young Ahn , Sang-Ryol Yang , Ki-Hyun Hwang
发明人： Sung-Hae Lee , Ju-Wan Lim , Jae-Young Ahn , Sang-Ryol Yang , Ki-Hyun Hwang
IPC分类号： H01L21/8247
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/4234 , Y10S438/954
摘要： In an embodiment, a method of manufacturing a charge-trapping dielectric and a silicon-oxide-nitride-oxide-silicon (SONOS)-type non-volatile semiconductor device includes forming the charge-trapping dielectric, and a first oxide layer including silicon oxide. A silicon nitride layer including silicon-rich nitride is formed by a cyclic chemical vapor deposition (CVD) process using a silicon source material and a nitrogen source gas. A second oxide layer is formed on the silicon nitride layer. Hence, the charge-trapping dielectric having good erase characteristics is formed. In the SONOS-type non-volatile semiconductor device including the charge-trapping dielectric, a data erase process may be stably performed.
摘要翻译：在一个实施例中，制造电荷俘获电介质和氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体器件的方法包括形成电荷俘获电介质和包含氧化硅的第一氧化物层。通过使用硅源材料和氮源气体的循环化学气相沉积（CVD）工艺形成包括富含硅的氮化物的氮化硅层。在氮化硅层上形成第二氧化物层。因此，形成具有良好擦除特性的电荷俘获电介质。在包含电荷捕获电介质的SONOS型非易失性半导体器件中，可以稳定地执行数据擦除处理。

5. 发明申请

US20080128788A1 Flash memory device including multilayer tunnel insulator and method of fabricating the same 失效
标题翻译：包括多层隧道绝缘体的闪存器件及其制造方法
公开(公告)号：US20080128788A1
公开(公告)日：2008-06-05
申请号：US12003992
申请日：2008-01-04
申请人： Sung-kweon Baek , Sang-ryol Yang , Si-young Choi , Bon-young Koo , Ki-hyun Hwang , Jin-tae Noh
发明人： Sung-kweon Baek , Sang-ryol Yang , Si-young Choi , Bon-young Koo , Ki-hyun Hwang , Jin-tae Noh
IPC分类号： H01L29/68 , H01L29/788 , H01L21/04
CPC分类号： H01L29/513 , H01L21/28273 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A flash memory device including a lower tunnel insulation layer on a substrate, an upper tunnel insulation layer on the lower tunnel insulation layer, and a P-type gate on the upper tunnel insulation layer, wherein the upper tunnel insulation layer includes an amorphous oxide layer.
摘要翻译：一种闪存装置，包括在基板上的下部隧道绝缘层，下部隧道绝缘层上的上部隧道绝缘层和上部隧道绝缘层上的P型栅极，其中上部隧道绝缘层包括无定形氧化物层。

6. 发明授权

US08309405B2 Three dimensional semiconductor memory device and method of fabricating the same 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US08309405B2
公开(公告)日：2012-11-13
申请号：US13228433
申请日：2011-09-08
申请人： Sang-Ryol Yang , Yoo-Chul Kong , Jin-Gyun Kim , Jae-Jin Shin , Jung-Ho Kim , Ji-Hoon Choi
发明人： Sang-Ryol Yang , Yoo-Chul Kong , Jin-Gyun Kim , Jae-Jin Shin , Jung-Ho Kim , Ji-Hoon Choi
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/44
CPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.
摘要翻译：形成垂直非易失性存储器件的方法可以包括形成电绝缘层，其包括夹在第一和第二模具层之间的牺牲层的复合材料。开口延伸穿过电绝缘层并暴露第一和第二模具层和牺牲层的内侧壁。开口的侧壁可以衬有电绝缘保护层，并且可以在开口内的电绝缘保护层的内侧壁上形成第一半导体层。然后可以从第一和第二模具层之间选择性地蚀刻牺牲层的至少一部分，从而在其中限定其中暴露电绝缘保护层的外侧壁的横向凹部。

7. 发明申请

US20110045667A1 Gate of a transistor and method of forming the same 审中-公开
标题翻译：晶体管的栅极及其形成方法
公开(公告)号：US20110045667A1
公开(公告)日：2011-02-24
申请号：US12926151
申请日：2010-10-28
申请人： Jin-Gyun Kim , Ki-Hyun Hwang , Sang-Ryol Yang
发明人： Jin-Gyun Kim , Ki-Hyun Hwang , Sang-Ryol Yang
IPC分类号： H01L21/28
CPC分类号： H01L21/823842 , H01L21/82345 , H01L21/823456 , H01L21/82385
摘要： A gate of a transistor includes a gate oxide layer formed on a semiconductor device, a first conductive layer pattern including polysilicon doped with boron and formed on the gate oxide layer, a diffusion preventing layer pattern including amorphous silicon formed by a chemical vapor deposition process using a reaction gas having trisilane (Si3H8) and formed on the first conductive layer pattern, and a second conductive layer pattern including metal silicide and formed on the diffusion preventing layer pattern. Since a gate of PMOS transistor includes a diffusion preventing layer having an excellent surface morphology, diffusion of impurities is sufficiently prevented. Thus, the threshold voltage of PMOS transistor may be reduced and threshold voltage distribution may be improved.
摘要翻译：晶体管的栅极包括形成在半导体器件上的栅极氧化层，包含掺杂有硼的多晶硅并形成在栅极氧化物层上的第一导电层图案，包括通过化学气相沉积工艺形成的非晶硅的扩散防止层图案，其使用形成在第一导电层图案上的具有丙硅烷（Si 3 H 8）的反应气体和形成在扩散防止层图案上的包含金属硅化物的第二导电层图案。由于PMOS晶体管的栅极包括具有优异表面形态的扩散防止层，因此充分防止了杂质的扩散。因此，可以降低PMOS晶体管的阈值电压，并且可以提高阈值电压分布。

8. 发明授权

US07723755B2 Semiconductor having buried word line cell structure and method of fabricating the same 有权
标题翻译：具有掩埋字线单元结构的半导体及其制造方法
公开(公告)号：US07723755B2
公开(公告)日：2010-05-25
申请号：US12003973
申请日：2008-01-04
申请人： Si-hyung Lee , Sang-ryol Yang , Myoung-bum Lee , Ki-hyun Hwang
发明人： Si-hyung Lee , Sang-ryol Yang , Myoung-bum Lee , Ki-hyun Hwang
IPC分类号： H01L27/00
CPC分类号： H01L27/10876 , H01L27/10891
摘要： Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce the height of the semiconductor device and to reduce the degradation of the oxide layer caused by chlorine ions from the application of a TiN metal gate, and a method of fabricating the semiconductor device. The semiconductor device may comprise a semiconductor substrate defined by a device isolation layer and comprising an active region including a trench and one or more recess channels, a gate isolation layer on the surface of the trench, a gate electrode layer on the surface of the gate isolation layer, and a word line by which the trench may be buried on the surface of the gate electrode layer.
摘要翻译：提供一种具有掩埋字线结构的半导体器件，其中栅极电极和字线可以被掩埋在衬底内以降低半导体器件的高度并且减少由来自应用的氯离子引起的氧化物层的劣化的TiN金属栅极，以及制造半导体器件的方法。半导体器件可以包括由器件隔离层限定的半导体衬底，并且包括有源区，包括沟槽和一个或多个凹陷通道，沟槽表面上的栅极隔离层，栅极表面上的栅极电极层隔离层以及沟槽可以埋在栅电极层的表面上的字线。

9. 发明申请

US20130065369A1 THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20130065369A1
公开(公告)日：2013-03-14
申请号：US13671948
申请日：2012-11-08
申请人： Sang-Ryol Yang , Yoo-Chul Kong , Jung-Ho Kim , Jin-Gyun Kim , Jae-Jin Shin , Ji-Hoon Choi
发明人： Sang-Ryol Yang , Yoo-Chul Kong , Jung-Ho Kim , Jin-Gyun Kim , Jae-Jin Shin , Ji-Hoon Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.
摘要翻译：形成垂直非易失性存储器件的方法可以包括形成电绝缘层，其包括夹在第一和第二模具层之间的牺牲层的复合材料。开口延伸穿过电绝缘层并暴露第一和第二模具层和牺牲层的内侧壁。开口的侧壁可以衬有电绝缘保护层，并且可以在开口内的电绝缘保护层的内侧壁上形成第一半导体层。然后可以从第一和第二模具层之间选择性地蚀刻牺牲层的至少一部分，从而在其中限定其中暴露电绝缘保护层的外侧壁的横向凹部。

10. 发明授权

US08330207B2 Flash memory device including multilayer tunnel insulator and method of fabricating the same 失效
标题翻译：包括多层隧道绝缘体的闪存器件及其制造方法
公开(公告)号：US08330207B2
公开(公告)日：2012-12-11
申请号：US12003992
申请日：2008-01-04
申请人： Sung-kweon Baek , Sang-ryol Yang , Si-young Choi , Bon-young Koo , Ki-hyun Hwang , Jin-tae Noh
发明人： Sung-kweon Baek , Sang-ryol Yang , Si-young Choi , Bon-young Koo , Ki-hyun Hwang , Jin-tae Noh
IPC分类号： H01L29/788 , H01L21/04
CPC分类号： H01L29/513 , H01L21/28273 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A flash memory device including a lower tunnel insulation layer on a substrate, an upper tunnel insulation layer on the lower tunnel insulation layer, and a P-type gate on the upper tunnel insulation layer, wherein the upper tunnel insulation layer includes an amorphous oxide layer.
摘要翻译：一种闪存装置，包括在基板上的下部隧道绝缘层，下部隧道绝缘层上的上部隧道绝缘层和上部隧道绝缘层上的P型栅极，其中上部隧道绝缘层包括无定形氧化物层。

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