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1. 发明授权

US08411482B2 Programmable read only memory 有权
标题翻译：可编程只读存储器
公开(公告)号：US08411482B2
公开(公告)日：2013-04-02
申请号：US12229117
申请日：2008-08-20
申请人： Zhanping Chen , Sarvesh Kulkarni , Kevin Zhang
发明人： Zhanping Chen , Sarvesh Kulkarni , Kevin Zhang
IPC分类号： G11C17/00 , G11C17/14 , G11C17/16 , G11C17/18
CPC分类号： G11C17/16 , G11C17/18
摘要： A memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is applied to a stack of first and second conductive layers. A first portion of the stack couples the program voltage to a terminal of the transistor in a cell. A second portion of the stack couples the program voltage to a terminal of the transistor in another cell.
摘要翻译：存储单元包括熔丝和至少一个晶体管。晶体管用于控制保险丝的编程或感测。将编程电压施加到第一和第二导电层的堆叠。堆叠的第一部分将编程电压耦合到单元中的晶体管的端子。堆叠的第二部分将编程电压耦合到另一个单元中的晶体管的端子。

2. 发明申请

US20100046269A1 Programmable read only memory 有权
标题翻译：可编程只读存储器
公开(公告)号：US20100046269A1
公开(公告)日：2010-02-25
申请号：US12229117
申请日：2008-08-20
申请人： Zhanping Chen , Sarvesh Kulkarni , Kevin Zhang
发明人： Zhanping Chen , Sarvesh Kulkarni , Kevin Zhang
IPC分类号： G11C17/00 , H01L21/82 , G11C11/34
CPC分类号： G11C17/16 , G11C17/18
摘要： An array of memory cells is disclosed. The memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is applied to a stack of first and second conductive layers. A first portion of the stack couples the program voltage to a terminal of the transistor in a cell. A second portion of the stack couples the program voltage to a terminal of the transistor in another cell.
摘要翻译：公开了一组存储器单元。存储单元包括熔丝和至少一个晶体管。晶体管用于控制保险丝的编程或感测。将编程电压施加到第一和第二导电层的堆叠。堆叠的第一部分将编程电压耦合到单元中的晶体管的端子。堆叠的第二部分将编程电压耦合到另一个单元中的晶体管的端子。

3. 发明申请

US20060069901A1 Apparatus and method for an address generation circuit 有权
标题翻译：地址生成电路的装置和方法
公开(公告)号：US20060069901A1
公开(公告)日：2006-03-30
申请号：US10956164
申请日：2004-09-30
申请人： Sanu Mathew , Mark Anders , Sarvesh Kulkarni , Ram Krishnamurthy
发明人： Sanu Mathew , Mark Anders , Sarvesh Kulkarni , Ram Krishnamurthy
IPC分类号： G06F12/04
CPC分类号： G06F7/507 , G06F7/508
摘要： A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logic 0 carry-in and a logic 1 carry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.
摘要翻译：一种用于地址产生电路的方法和装置。在一个实施例中，该方法包括计算由多个逻辑地址分量形成的传播信号和生成信号的预定位数的至少一组的进位。一旦计算了进位，则为逻辑0进位和逻辑1进位产生多个条件和。随后，从多个条件和中选出一个和，以在第二阶段中从第一阶段的逻辑地址分量和有效地址的第二部分形成有效地址的第一部分。在一个实施例中，根据一个实施例，使用产生四分之一载波的完全动态的高性能稀疏树加法器电路来形成地址生成电路。描述和要求保护其他实施例。

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