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1. 发明授权

US10073677B2 Mixed-radix carry-lookahead adder architecture 有权
公开(公告)号：US10073677B2
公开(公告)日：2018-09-11
申请号：US14740841
申请日：2015-06-16
申请人： Microsoft Technology Licensing, LLC
发明人： Nathan Trent Josephsen , Steven Brian Shauck
IPC分类号： G06F7/508 , G06F7/501
CPC分类号： G06F7/508 , G06F7/501
摘要： Embodiments described herein are directed to mixed-radix carry-lookahead adders and methods performed thereby. The mixed-radix carry-lookahead adder includes an multiple carry-lookahead stages, where each stage may be of a different radix. Each stage operates on input bits, creating and implementing propagate and generate signals for each bit. The carry-lookahead stages also compute an XOR of the inputs that is forwarded to a final carry-lookahead stage. The elements of the initial and subsequent carry-lookahead stages are arranged such that each of the propagate and generate output signals passes through a minimal number of passive transmission lines. The final stage of the mixed-radix carry-lookahead adder includes an XOR logic gate configured to receive the generate output from an intermediate carry-lookahead stage and XOR the generate output received from the intermediate carry-lookahead stage with the computed XOR signal forwarded from the initial carry-lookahead stage to produce a sum of the input bits.

2. 发明授权

US09740483B2 Vector checksum instruction 有权
公开(公告)号：US09740483B2
公开(公告)日：2017-08-22
申请号：US15294848
申请日：2016-10-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jonathan D. Bradbury , Eric M. Schwarz
IPC分类号： G06F9/30 , G06F11/10 , G06F7/508
CPC分类号： G06F9/30036 , G06F7/508 , G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/30098 , G06F9/3013 , G06F11/1004
摘要： A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.

3. 发明申请

US20170031683A1 VECTOR CHECKSUM INSTRUCTION 有权
标题翻译：矢量检查指示
公开(公告)号：US20170031683A1
公开(公告)日：2017-02-02
申请号：US15295141
申请日：2016-10-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jonathan D. Bradbury , Eric M. Schwarz
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/508 , G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/30098 , G06F9/3013 , G06F11/1004
摘要： A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.
摘要翻译：矢量校验和指令。来自第二个操作数的元素逐个加入，以获得第一个结果。添加包括执行一个或多个结束周围的附加操作。第一个结果被放置在指令的第一个操作数的元素中。在每次添加元素之后，如果有的话，将所述和的选择位置的进位添加到第一操作数的元素中的选定位置。

4. 发明申请

US20160239268A1 ADDING APPARATUS USING TIME INFORMATION AND A METHOD THEREOF 审中-公开
标题翻译：使用时间信息添加设备及其方法
公开(公告)号：US20160239268A1
公开(公告)日：2016-08-18
申请号：US14621016
申请日：2015-02-12
申请人： Korea Advanced Institute of Science and Technology
发明人： Seong Hwan CHO , Dong In KIM
IPC分类号： G06F7/508
CPC分类号： G06F7/508
摘要： An adding apparatus according to an example of the present invention comprises: a time adder for outputting a time addition signal using time information of the first input signal and time information of the second input signal, if a first input signal synchronized according to a unit time delay and a second input signal synchronized with the unit time delay; and a carry digit processor for outputting a carry generation signal by conducting a carry-lookahead operation corresponding to the time addition signal according to the unit time delay.
摘要翻译：根据本发明的示例的附加装置包括：时间加法器，用于使用第一输入信号的时间信息和第二输入信号的时间信息输出时间相加信号，如果第一输入信号根据单位时间同步延迟和与单位时间延迟同步的第二输入信号; 以及进位数处理器，用于通过根据单位时间延迟进行与时间相加信号相对应的进位查找操作来输出进位发生信号。

5. 发明申请

US20110093518A1 NEAR OPTIMAL CONFIGURABLE ADDER TREE FOR ARBITRARY SHAPED 2D BLOCK SUM OF ABSOLUTE DIFFERENCES (SAD) CALCULATION ENGINE 有权
标题翻译：邻近的最佳配置ADDER TREE用于绝对形状二维块的绝对差异（SAD）计算引擎
公开(公告)号：US20110093518A1
公开(公告)日：2011-04-21
申请号：US12581482
申请日：2009-10-19
申请人： Karthikeyan Vaithianathan , Arvind Sudarsanam
发明人： Karthikeyan Vaithianathan , Arvind Sudarsanam
IPC分类号： G06F7/50
CPC分类号： G06F7/544 , G06F7/505 , G06F7/508 , G06F17/10 , G06F2207/5442
摘要： Embodiments of a near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine are generally described herein. Other embodiments may be described and claimed. In some embodiments, a configurable two-dimensional adder tree architecture for computing a sum of absolute differences (SAD) for various block sizes up to 16 by 16 comprises a first stage of one-dimensional adder trees and a second stage of one-dimensional adder trees, wherein each one-dimensional adder tree comprises an input routing network, a plurality of adder units, and an output routing network.
摘要翻译：这里通常描述用于任意形状的2D块绝对差（SAD）计算引擎的近似最佳可配置加法器树的实施例。可以描述和要求保护其他实施例。在一些实施例中，用于计算高达16×16的各种块大小的绝对差（SAD）之和的可配置二维加法器树结构包括一维加法器树的第一级和一维加法器的第二级树，其中每个一维加法器树包括输入路由网络，多个加法器单元和输出路由网络。

6. 发明授权

US07822799B1 Adder-rounder circuitry for specialized processing block in programmable logic device 有权
标题翻译：用于可编程逻辑器件中专用处理块的加法器电路
公开(公告)号：US07822799B1
公开(公告)日：2010-10-26
申请号：US11426403
申请日：2006-06-26
申请人： Martin Langhammer , Triet M. Nguyen , Yi-Wen Lin
发明人： Martin Langhammer , Triet M. Nguyen , Yi-Wen Lin
IPC分类号： G06F7/38
CPC分类号： G06F7/509 , G06F7/49963 , G06F7/5016 , G06F7/508
摘要： Adder/rounder circuitry for use in a programmable logic device computes a rounded sum quickly, and ideally within one clock cycle. The rounding position is selectable within a range of bit positions. In an input stage, for each bit position in that range, bits from both addends and a rounding bit are processed, while for each bit position outside that range only bits from both addends are processed. The input stage processing aligns its output in a common format for bits within and outside the range. The input processing may include 3:2 compression for bit positions within the range and 2:2 compression for bit positions outside the range, so that further processing is performed for all bit positions on a sum vector and a carry vector. Computation of the sum proceeds substantially simultaneously with and without the rounding input, and rounding logic makes a selection later in the computation.
摘要翻译：用于可编程逻辑器件的加法器/圆形电路可以快速计算舍入的并且理想地在一个时钟周期内计算。舍入位置可在位位置范围内选择。在输入级中，对于该范围内的每个位位置，处理来自两个加数和舍入位的位，而对于该范围之外的每个位位置，只处理来自两个加数的位。输入级处理以范围内和外的位的通用格式对齐其输出。输入处理可以包括在该范围内的比特位置的3：2压缩，以及在该范围之外的比特位置的2：2压缩，使得对和矢量和进位向量的所有比特位置执行进一步的处理。总和的计算基本上与舍入输入同时进行，并且舍入逻辑在计算中稍后进行选择。

7. 发明授权

US07711761B2 Method and system for digital signal processing, program product therefor 有权
标题翻译：数字信号处理方法与系统，程序产品
公开(公告)号：US07711761B2
公开(公告)日：2010-05-04
申请号：US11179027
申请日：2005-07-11
申请人： Daniele Lo Iacono , Marco Ronchi
发明人： Daniele Lo Iacono , Marco Ronchi
IPC分类号： G06F15/00
CPC分类号： G06F7/5332 , G06F7/4824 , G06F7/49994 , G06F7/508 , H03M7/04
摘要： A system, such as, e.g., a multiplier, for processing digital signals by using digital signals in the Canonic Signed Digit representation, the system including an input element to make the digital signals available in the Binary Canonic Signed Digit representation, a converter to convert the digital signals into Canonic Signed Digit representation for use in processing. The input element may be a memory where the signals are stored in the Binary Canonic Signed Digit representation. Alternatively, the input element is adapted to be fed with digital signals in the two's complement representation, and includes at least one converter to convert the digital signals from the two's complement representation into the Binary Canonic Signed Digit representation. This preferably occurs via the T2I transformation, which leads to generating signals in the Canonic Signed Digit representation, which are then converted to the Binary Canonic Signed Digit representation.
摘要翻译：一种系统，例如乘法器，用于通过在加农生物签名数字表示中使用数字信号来处理数字信号，所述系统包括用于使得二进制加拿大签名数字表示中的数字信号可用的输入元件，转换器数字信号转换成Canonic Signed Digit表示用于处理。输入元件可以是其中信号被存储在二进制加拿大签名数字表示中的存储器。或者，输入元件适于以二进制补码表示中的数字信号馈送，并且包括至少一个转换器，用于将来自二进制补码表示的数字信号转换为二进制加法符号数字表示。这优选地通过T2I变换发生，这导致在加农声有符号数字表示中产生信号，然后将其转换为二进制加法符号数字表示。

8. 发明授权

US07685215B1 Fast-carry arithmetic circuit using a multi-input look-up table 有权
标题翻译：使用多输入查找表的快速运算算术电路
公开(公告)号：US07685215B1
公开(公告)日：2010-03-23
申请号：US11257137
申请日：2005-10-24
申请人： Brian Gaide , Xiaojie He
发明人： Brian Gaide , Xiaojie He
IPC分类号： G06F7/38 , G06F7/50
CPC分类号： G06F7/508
摘要： In one embodiment of the invention, programmable circuits, such as FPGAs, may be used to implement different types of functions, such as a multi-bit adder, using look-up table (LUT) circuits as their building blocks. Efficient generation of carry-out signals and fast-carry generation signals using available SRAM cells in the various embodiments of the LUT circuit can reduce and/or eliminate area-inefficient look-ahead carry logic without a significant delay in signal generation.
摘要翻译：在本发明的一个实施例中，诸如FPGA之类的可编程电路可以用于实现不同类型的功能，例如使用查找表（LUT）电路作为其构建块的多位加法器。在LUT电路的各种实施例中，利用可用的SRAM单元有效地产生进位信号和快速携带产生信号可以减少和/或消除无效率的先行进位逻辑，而不会产生显着的信号延迟。

9. 发明授权

US07111034B2 Carry foreknowledge adder 失效
标题翻译：携带预知加法器
公开(公告)号：US07111034B2
公开(公告)日：2006-09-19
申请号：US10352903
申请日：2003-01-29
申请人： Shinichi Ozawa
发明人： Shinichi Ozawa
IPC分类号： G06F7/508
CPC分类号： G06F7/508 , G06F2207/5063
摘要： A carry foreknowledge adder comprise an adding circuit for adding binary numbers A and B of n bits; and a plurality of carry foreknowledge circuit blocks that respectively corresponding to divisional portions obtained by dividing the A and the B through setting a unit length. Each carry foreknowledge circuit block has a plurality of arithmetic operating portions (j, i) in correspondence to each bit, that respectively receive a block carry Cin corresponding to the most significant bit in a lower the carry foreknowledge circuit block from the lower carry foreknowledge circuit block corresponding to lower divisional portion, each arithmetic operating portion arithmetically determining the carry Ci on the basis of the block carry Cin, and outputting the carry Ci to the adding circuit, and each arithmetic operating portion (j, i) has a logic circuit portion which receives the block carry Cin and is arranged on an output terminal side.
摘要翻译：进位预知加法器包括用于加入n位的二进制数A和B的加法电路; 以及分别对应于通过设置单位长度而通过划分A和B获得的分割部分的多个进位预知电路块。每个进位预知电路块具有对应于每个位的多个算术运算部分（j，i），分别在较低的进位预知中分别接收对应于最高有效位的中的块进位C < 电路块与较低分位部分相对应的较低进位预知电路块，每个算术运算部分基于中的块进位C 算术确定进位C i，向加法电路输出进位C i i i，并且每个算术运算部分（j，i）都具有逻辑电路部分，其接收中的块进位C＆amp; 输出端子侧。

10. 发明授权

US07093105B2 Method and apparatus for determining availability of a queue to which a program step is issued out of program order 有权
标题翻译：用于确定从程序顺序发出程序步骤的队列的可用性的方法和装置
公开(公告)号：US07093105B2
公开(公告)日：2006-08-15
申请号：US10779503
申请日：2004-02-13
申请人： David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer
发明人： David Arthur James Webb, Jr. , James Keller , Derrick R. Meyer
IPC分类号： G06F9/30
CPC分类号： G06F7/76 , G06F7/4824 , G06F7/508 , G06F7/535 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F2207/5352
摘要： A method and apparatus to allow program steps in an issue queue to be sent to the execution queue in a non program order provides reduced stall by allowing out of program order steps to be executed as needed resources become available. The method uses a modulus operation to preassign locations in the execution queues, and keep the entries in proper program order. The method employs an additional bit to represent the modules result (value) and may also utilize a load store number mapping memory to increase execution speed. With such an arrangement a computer system may decrease the lost performance due to waiting for required resource (i.e., memory or bus) availability for the current instruction, by issuing instructions for which the memory or bus resource is available even though the instruction is not the next one in the original program order. Thus the present invention allows memory reference instructions to issue as resources are available.
摘要翻译：允许以非程序顺序将发布队列中的程序步骤发送到执行队列的方法和装置通过允许在需要的资源变得可用时执行程序顺序步骤来减少停止。该方法使用模数运算来对执行队列中的位置进行预分配，并使条目保持正确的程序顺序。该方法使用附加位来表示模块结果（值），并且还可以利用加载存储器号映射存储器来增加执行速度。通过这样的布置，由于等待当前指令的所需资源（即，存储器或总线）可用性，计算机系统可以通过发出存储器或总线资源可用的指令来减少丢失的性能，即使该指令不是下一个在原程序中。因此，本发明允许存储器参考指令在资源可用时发布。

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