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1. 发明授权

US08497175B2 Method of fabricating FinFET devices 有权
标题翻译： FinFET器件的制造方法
公开(公告)号：US08497175B2
公开(公告)日：2013-07-30
申请号：US12766055
申请日：2010-04-23
申请人： Jae-Rok Kahng , Makoto Yoshida , Se-Myeong Jang
发明人： Jae-Rok Kahng , Makoto Yoshida , Se-Myeong Jang
IPC分类号： H01L21/8234
CPC分类号： H01L29/7851 , H01L29/42384 , H01L29/66795
摘要： A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET.
摘要翻译：使用光致抗蚀剂掩模图案制造半导体器件，并且选择性地去除单元区域和外围电路区域中的衬里氮化物层的部分。形成改进的FinFET以减小由相邻栅极线在单元区域中传输的信号的影响。在形成改进的FinFET的同时，在芯区域和周边区域分别形成双FinFET和基本上平面的MOSFET。

2. 发明授权

US08293644B2 Methods of manufacturing a semiconductor memory device 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US08293644B2
公开(公告)日：2012-10-23
申请号：US12656969
申请日：2010-02-22
申请人： Se-myeong Jang , Min-sung Kang
发明人： Se-myeong Jang , Min-sung Kang
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76804 , H01L21/76814 , H01L21/76897 , H01L23/485 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a semiconductor include forming an insulation layer over a semiconductor substrate in which a first region and a second region are defined. A storage node contact (SNC) that passes through the insulation layer is formed and is electrically connected to the first region. A conductive layer that passes through the insulation layer is deposited and is electrically connected to the second region on the insulation layer and the SNC. A bit line is formed by removing an upper portion of the conductive layer, an upper portion of the insulation layer and an upper portion of the SNC until the SNC and the conductive layer are electrically separated from each other, wherein the bit line is a remaining part of the conductive layer.
摘要翻译：形成半导体的方法包括在其中限定了第一区域和第二区域的半导体衬底上形成绝缘层。通过绝缘层的存储节点接触（SNC）形成并电连接到第一区域。沉积穿过绝缘层的导电层并与绝缘层和SNC上的第二区电连接。通过去除导电层的上部，绝缘层的上部和SNC的上部形成位线，直到SNC和导电层彼此电分离，其中位线是剩余的导电层的一部分。

3. 发明授权

US07952140B2 Methods of fabricating semiconductor devices having multiple channel transistors and semiconductor devices fabricated thereby 有权
标题翻译：制造具有多个沟道晶体管和由此制造的半导体器件的半导体器件的方法
公开(公告)号：US07952140B2
公开(公告)日：2011-05-31
申请号：US12705011
申请日：2010-02-12
申请人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Hyun-Ju Sung , Hui-Jung Kim , Chang-Hoon Jeon
发明人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Hyun-Ju Sung , Hui-Jung Kim , Chang-Hoon Jeon
IPC分类号： H01L29/66
CPC分类号： H01L27/105 , H01L21/823412 , H01L21/823437 , H01L21/823481 , H01L27/1052
摘要： In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are disposed within the first region, and each of the semiconductor pillars has at least one recessed region therein. At least one gate structure may be disposed across the recessed regions, which crosses the semiconductor pillars and extends onto the isolation region.
摘要翻译：在制造具有多个沟道晶体管和由此制造的半导体器件的半导体器件的方法中，半导体器件包括设置在半导体衬底内并限定第一区域的隔离区域。与第一区域自对准并且彼此间隔开的多个半导体柱设置在第一区域内，并且每个半导体柱在其中具有至少一个凹陷区域。至少一个栅极结构可以设置在穿过半导体柱并且延伸到隔离区上的凹陷区域之间。

4. 发明授权

US07700445B2 Method for fabricating multiple FETs of different types 有权
标题翻译：制造不同类型多个FET的方法
公开(公告)号：US07700445B2
公开(公告)日：2010-04-20
申请号：US11804875
申请日：2007-05-21
申请人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Chul Lee , Keun-Nam Kim , Hyun-Ju Sung , Hui-Jung Kim , Kyoung-Ho Jung
发明人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Chul Lee , Keun-Nam Kim , Hyun-Ju Sung , Hui-Jung Kim , Kyoung-Ho Jung
IPC分类号： H01L21/336
CPC分类号： H01L21/823412
摘要： For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.
摘要翻译：为了制造多个场效应晶体管（FET），第一导电层沉积在半导体衬底的第一和第二有源区上。在第二有源区上形成第一导电层以形成模具结构。在模具结构之间形成掩模结构。使用掩模结构或使用形成在模具结构的侧壁处的间隔来形成第二有源区，以形成翅片型场效应晶体管的多个鳍。在第一有源区上图案化第一导电层以形成不同类型的另一场效应晶体管的栅极。

5. 发明申请

US20080001235A1 Integrated Circuit Devices Having Uniform Silicide Junctions 有权
标题翻译：具有均匀硅化物结合的集成电路器件
公开(公告)号：US20080001235A1
公开(公告)日：2008-01-03
申请号：US11853361
申请日：2007-09-11
申请人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
发明人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
IPC分类号： H01L29/78
CPC分类号： H01L29/41783 , H01L21/28247 , H01L21/28518 , H01L21/823418 , H01L27/105 , H01L27/10873 , H01L27/10894 , H01L29/41775 , H01L29/6653 , H01L29/6656 , H01L29/66628
摘要： Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.
摘要翻译：提供集成电路器件，其包括集成电路衬底和集成电路衬底上的栅极。门有侧壁。阻挡层间隔件设置在栅极的侧壁上。阻挡层间隔物的一部分从栅极的侧壁突出，暴露出面向集成电路基板的阻挡层隔离物的下表面。在从栅极的侧壁突出的阻挡层隔离物的部分上提供硅化物层。

6. 发明申请

US20070235785A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070235785A1
公开(公告)日：2007-10-11
申请号：US11697641
申请日：2007-04-06
申请人： Jae-Rok KAHNG , Makoto YOSHIDA , Se-Myeong JANG
发明人： Jae-Rok KAHNG , Makoto YOSHIDA , Se-Myeong JANG
IPC分类号： H01L27/108
CPC分类号： H01L29/7851 , H01L29/42384 , H01L29/66795
摘要： A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET.
摘要翻译：使用光致抗蚀剂掩模图案制造半导体器件，并且选择性地去除单元区域和外围电路区域中的衬里氮化物层的部分。形成改进的FinFET以减小由相邻栅极线在单元区域中传输的信号的影响。在形成改进的FinFET的同时，在芯区域和周边区域分别形成双FinFET和基本上平面的MOSFET。

7. 发明授权

US07223649B2 Method of fabricating transistor of DRAM semiconductor device 有权
标题翻译：制造DRAM半导体器件晶体管的方法
公开(公告)号：US07223649B2
公开(公告)日：2007-05-29
申请号：US10922055
申请日：2004-08-18
申请人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
发明人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/8242
CPC分类号： H01L21/823878 , H01L21/28185 , H01L21/28202 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L27/10873 , H01L27/10894 , H01L29/513 , H01L29/518
摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.
摘要翻译：实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极地区。实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。

8. 发明授权

US06974752B2 Methods of fabricating integrated circuit devices having uniform silicide junctions 有权
标题翻译：制造具有均匀硅化物结的集成电路器件的方法
公开(公告)号：US06974752B2
公开(公告)日：2005-12-13
申请号：US10422430
申请日：2003-04-24
申请人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
发明人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/417 , H01L29/78
CPC分类号： H01L29/41783 , H01L21/28247 , H01L21/28518 , H01L21/823418 , H01L27/105 , H01L27/10873 , H01L27/10894 , H01L29/41775 , H01L29/6653 , H01L29/6656 , H01L29/66628
摘要： A gate having sidewalls is formed on an integrated circuit substrate. A barrier layer spacer is formed on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is formed on the portion of the barrier layer spacer protruding from the sidewalls of the gate. Related devices are also provided.
摘要翻译：具有侧壁的栅极形成在集成电路基板上。在栅极的侧壁上形成阻挡层间隔物。阻挡层间隔物的一部分从栅极的侧壁突出，暴露出面向集成电路基板的阻挡层隔离物的下表面。在从栅极的侧壁突出的阻挡层隔离物的部分上形成硅化物层。还提供了相关设备。

9. 发明授权

US06656790B2 Method for manufacturing a semiconductor device including storage nodes of capacitor 有权
标题翻译：用于制造包括电容器的存储节点的半导体器件的方法
公开(公告)号：US06656790B2
公开(公告)日：2003-12-02
申请号：US10078885
申请日：2002-02-19
申请人： Se-myeong Jang , Ki-nam Kim , Hong-sik Jeong , Yoo-sang Hwang
发明人： Se-myeong Jang , Ki-nam Kim , Hong-sik Jeong , Yoo-sang Hwang
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L21/76895 , H01L21/76897 , H01L27/10814 , H01L28/91
摘要： A semiconductor device including storage nodes of a capacitor and a method for manufacturing the same are provided. Bit lines are formed on a semiconductor substrate, and protection layers are formed to cover and protect the bit lines. Conductive contact pads are formed between the bit lines and are level with the top surfaces of the protection layers. A node supporting layer is formed to cover the conductive contact pads and the protection layers. An etching stopper is formed on the node supporting layer. The mold layer, the etching stopper, and the node supporting layer are patterned, thereby forming opening holes exposing the conductive pads. Storage nodes are formed in the opening holes and have the shape of the profile of the opening holes. The mold layer exposed by the storage nodes is removed, thereby exposing the outer wall of each of the storage nodes positioned above the etching stopper.
摘要翻译：提供了包括电容器的存储节点的半导体器件及其制造方法。位线形成在半导体衬底上，形成保护层以覆盖并保护位线。导电接触焊盘形成在位线之间并与保护层的顶表面平齐。形成节点支撑层以覆盖导电接触焊盘和保护层。在节点支撑层上形成蚀刻止挡件。模塑层，蚀刻阻挡层和节点支撑层被图案化，从而形成露出导电焊盘的开孔。存储节点形成在开孔中并且具有开孔的轮廓的形状。由存储节点露出的模具层被去除，从而暴露位于蚀刻停止器上方的每个存储节点的外壁。

10. 发明申请

US20120202336A1 METHOD OF FORMING AN ISOLATION STRUCTURE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE 有权
标题翻译：形成隔离结构的方法和形成半导体器件的方法
公开(公告)号：US20120202336A1
公开(公告)日：2012-08-09
申请号：US13362142
申请日：2012-01-31
申请人： Joo-Sung PARK , Se-Myeong Jang , Gil-Sub Kim
发明人： Joo-Sung PARK , Se-Myeong Jang , Gil-Sub Kim
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A method of forming an isolation structure includes forming a trench at an upper portion of a substrate, forming a first oxide layer on an inner wall of the trench, oxidizing a portion of the substrate adjacent to the trench to form a second oxide layer such that the portion of the substrate adjacent to the trench has the first oxide layer thereon, forming a nitride layer on the first oxide layer, and forming an insulation layer pattern on the nitride layer such that the insulation layer pattern fills a remaining portion of the trench.
摘要翻译：形成隔离结构的方法包括在衬底的上部形成沟槽，在沟槽的内壁上形成第一氧化物层，氧化邻近沟槽的衬底的一部分以形成第二氧化物层，使得与沟槽相邻的衬底部分具有第一氧化物层，在第一氧化物层上形成氮化物层，并在氮化物层上形成绝缘层图案，使得绝缘层图案填充沟槽的剩余部分。

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