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1. 发明申请

US20120023345A1 MANAGING CURRENT AND POWER IN A COMPUTING SYSTEM 有权
标题翻译：管理计算系统中的电流和功率
公开(公告)号：US20120023345A1
公开(公告)日：2012-01-26
申请号：US12840813
申请日：2010-07-21
申请人： Samuel D. Naffziger , Sebastien J. Nussbaum
发明人： Samuel D. Naffziger , Sebastien J. Nussbaum
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3206 , G06F1/3243 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D10/24
摘要： A system and method for efficient power transfer on a die. A semiconductor chip comprises on a die two or more computation units (CUs) utilizing at least two different voltage regulators and a power manager. The power manager reallocates power credits across the die when it detects an activity level of a given CU is below a given threshold. In response to receiving a corresponding number of donated power credits, each of the one or more selected CUs maintains a high activity level with a high performance P-state. When a corresponding workload increases, each CU maintains operation and an average power consumption corresponding to the high performance P-state by alternating between at least two different operational voltages. When the operational voltage drops during the alternation, the current drawn by the particular CU may exceed a given current limit. The power manager detects this current limit is exceeded and accordingly reallocates the power credits across the die.
摘要翻译：一种用于模具上有效功率传输的系统和方法。半导体芯片在裸片上包括利用至少两个不同的电压调节器和功率管理器的两个或多个计算单元（CU）。电源管理器在检测到给定CU的活动电平低于给定阈值时，通过芯片重新分配功率信息。响应于接收到相应数量的捐赠功率信用，所述一个或多个所选择的CU中的每一个保持具有高性能P状态的高活动级别。当相应的工作量增加时，每个CU通过在至少两个不同的操作电压之间交替来维持对应于高性能P状态的操作和平均功耗。当交变期间工作电压下降时，由特定CU吸引的电流可能会超过给定的电流限制。电源管理器检测到超出此电流限制，从而重新分配芯片上的功率信息。

2. 发明授权

US08910177B2 Dynamic mapping of logical cores 有权
标题翻译：逻辑内核的动态映射
公开(公告)号：US08910177B2
公开(公告)日：2014-12-09
申请号：US13087206
申请日：2011-04-14
申请人： Michael J. Osborn , Sebastien J. Nussbaum
发明人： Michael J. Osborn , Sebastien J. Nussbaum
IPC分类号： G06F9/50 , G06F9/455
CPC分类号： G06F9/5088 , G06F9/5077 , G06F9/5094 , Y02D10/22
摘要： A processor that dynamically remaps logical cores to physical cores is disclosed. In one embodiment, the processor includes a plurality of physical cores, and is configured to store a mapping of logical cores to the plurality of physical cores. The processor further includes an assignment unit configured to remap the logical cores to the plurality of physical cores subsequent to a boot process of the processor. In some embodiments, the assignment unit is configured to remap the logical cores in response to receiving an indication that one or more of the plurality of physical cores have entered an idle state. The processor may be configured to load a first of the plurality of physical cores with an execution state of a second of the plurality of physical cores upon the first physical core exiting an idle state.
摘要翻译：公开了一种将逻辑内核动态重映射到物理内核的处理器。在一个实施例中，处理器包括多个物理核心，并且被配置为将逻辑核心的映射存储到多个物理核心。处理器还包括分配单元，其被配置为在处理器的引导过程之后将逻辑核重新映射到多个物理核。在一些实施例中，分配单元被配置为响应于接收到多个物理核中的一个或多个已经进入空闲状态的指示来重新映射逻辑核。所述处理器可以被配置为在所述第一物理核离开空闲状态时，以所述多个物理核心中的第二物理核心的执行状态来加载所述多个物理核心中的第一物理核心。

3. 发明授权

US08510582B2 Managing current and power in a computing system 有权
标题翻译：管理计算系统中的当前和功率
公开(公告)号：US08510582B2
公开(公告)日：2013-08-13
申请号：US12840813
申请日：2010-07-21
申请人： Samuel D. Naffziger , Sebastien J. Nussbaum
发明人： Samuel D. Naffziger , Sebastien J. Nussbaum
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3206 , G06F1/3243 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D10/24
摘要： A system and method for efficient power transfer on a die. A semiconductor chip comprises on a die two or more computation units (CUs) utilizing at least two different voltage regulators and a power manager. The power manager reallocates power credits across the die when it detects an activity level of a given CU is below a given threshold. In response to receiving a corresponding number of donated power credits, each of the one or more selected CUs maintains a high activity level with a high performance P-state. When a corresponding workload increases, each CU maintains operation and an average power consumption corresponding to the high performance P-state by alternating between at least two different operational voltages. When the operational voltage drops during the alternation, the current drawn by the particular CU may exceed a given current limit. The power manager detects this current limit is exceeded and accordingly reallocates the power credits across the die.
摘要翻译：一种用于模具上有效功率传输的系统和方法。半导体芯片在裸片上包括利用至少两个不同的电压调节器和功率管理器的两个或多个计算单元（CU）。电源管理器在检测到给定CU的活动电平低于给定阈值时，通过芯片重新分配功率信息。响应于接收到相应数量的捐赠功率信用，所述一个或多个所选择的CU中的每一个保持具有高性能P状态的高活动级别。当相应的工作量增加时，每个CU通过在至少两个不同的操作电压之间交替来维持对应于高性能P状态的操作和平均功耗。当交变期间工作电压下降时，由特定CU吸引的电流可能会超过给定的电流限制。电源管理器检测到超出此电流限制，从而重新分配芯片上的功率信息。

4. 发明申请

US20100122101A1 METHOD AND APPARATUS FOR REGULATING POWER CONSUMPTION 有权
标题翻译：调节功耗的方法和装置
公开(公告)号：US20100122101A1
公开(公告)日：2010-05-13
申请号：US12268531
申请日：2008-11-11
申请人： Samuel D. Naffziger , Sebastien J. Nussbaum
发明人： Samuel D. Naffziger , Sebastien J. Nussbaum
IPC分类号： G06F1/30
CPC分类号： G06F1/206 , G06F1/3203 , G06F9/50 , Y02D10/16 , Y02D10/22
摘要： A method for controlling power consumption while maximizing processor performance. The method includes, for a time interval of operation in a first operational state, determining an amount of power consumed during by one or more cores of a processor, calculating, a power error based on the amount of power consumed in the time interval, obtaining a power error term for the interval by adding the power error to a power error term from a previous time interval, and comparing the power error term to at least a first error threshold. If the power error term is outside a range defined at least in part by the first error threshold, the method exits the first operational state and enters a second operational state. If the power error term is within the range defined at least in part by the first error threshold, operation continues in the first operational state.
摘要翻译：一种在最大化处理器性能的同时控制功耗的方法。该方法包括：在第一操作状态下的操作的时间间隔中，确定处理器的一个或多个核心期间消耗的功率量，基于在该时间间隔中消耗的功率量来计算功率误差，获得通过将功率误差添加到来自前一时间间隔的功率误差项，以及将功率误差项与至少第一误差阈值进行比较来计算间隔的功率误差项。如果功率误差项在至少部分由第一误差阈值限定的范围之外，则该方法退出第一操作状态并进入第二操作状态。如果功率误差项在至少部分地由第一误差阈值限定的范围内，则操作在第一操作状态下继续。

5. 发明申请

US20120266179A1 DYNAMIC MAPPING OF LOGICAL CORES 有权
标题翻译：逻辑曲线的动态映射
公开(公告)号：US20120266179A1
公开(公告)日：2012-10-18
申请号：US13087206
申请日：2011-04-14
申请人： Michael J. Osborn , Sebastien J. Nussbaum
发明人： Michael J. Osborn , Sebastien J. Nussbaum
IPC分类号： G06F9/46
CPC分类号： G06F9/5088 , G06F9/5077 , G06F9/5094 , Y02D10/22
摘要： A processor that dynamically remaps logical cores to physical cores is disclosed. In one embodiment, the processor includes a plurality of physical cores, and is configured to store a mapping of logical cores to the plurality of physical cores. The processor further includes an assignment unit configured to remap the logical cores to the plurality of physical cores subsequent to a boot process of the processor. In some embodiments, the assignment unit is configured to remap the logical cores in response to receiving an indication that one or more of the plurality of physical cores have entered an idle state. The processor may be configured to load a first of the plurality of physical cores with an execution state of a second of the plurality of physical cores upon the first physical core exiting an idle state.
摘要翻译：公开了一种将逻辑内核动态重映射到物理内核的处理器。在一个实施例中，处理器包括多个物理核心，并且被配置为将逻辑核心的映射存储到多个物理核心。处理器还包括分配单元，其被配置为在处理器的引导过程之后将逻辑核重新映射到多个物理核。在一些实施例中，分配单元被配置为响应于接收到多个物理核中的一个或多个已经进入空闲状态的指示来重新映射逻辑核。所述处理器可以被配置为在所述第一物理核离开空闲状态时，以所述多个物理核心中的第二物理核心的执行状态来加载所述多个物理核心中的第一物理核心。

6. 发明授权

US08195962B2 Method and apparatus for regulating power consumption 有权
标题翻译：调节功耗的方法和装置
公开(公告)号：US08195962B2
公开(公告)日：2012-06-05
申请号：US12268531
申请日：2008-11-11
申请人： Samuel D. Naffziger , Sebastien J. Nussbaum
发明人： Samuel D. Naffziger , Sebastien J. Nussbaum
IPC分类号： G06F1/32 , G06F1/26 , G06F11/30
CPC分类号： G06F1/206 , G06F1/3203 , G06F9/50 , Y02D10/16 , Y02D10/22
摘要： A method for controlling power consumption while maximizing processor performance. The method includes, for a time interval of operation in a first operational state, determining an amount of power consumed during by one or more cores of a processor, calculating, a power error based on the amount of power consumed in the time interval, obtaining a power error term for the interval by adding the power error to a power error term from a previous time interval, and comparing the power error term to at least a first error threshold. If the power error term is outside a range defined at least in part by the first error threshold, the method exits the first operational state and enters a second operational state. If the power error term is within the range defined at least in part by the first error threshold, operation continues in the first operational state.
摘要翻译：一种在最大化处理器性能的同时控制功耗的方法。该方法包括：在第一操作状态下的操作的时间间隔中，确定处理器的一个或多个核心期间消耗的功率量，基于在该时间间隔中消耗的功率量来计算功率误差，获得通过将功率误差添加到来自前一时间间隔的功率误差项，以及将功率误差项与至少第一误差阈值进行比较来计算间隔的功率误差项。如果功率误差项在至少部分由第一误差阈值限定的范围之外，则该方法退出第一操作状态并进入第二操作状态。如果功率误差项在至少部分地由第一误差阈值限定的范围内，则操作在第一操作状态下继续。

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