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1. 发明授权

US09245608B2 Thermally tolerant perpendicular magnetic anisotropy coupled elements for spin-transfer torque switching device 有权
标题翻译：用于自旋传输转矩开关装置的耐热垂直磁各向异性耦合元件
公开(公告)号：US09245608B2
公开(公告)日：2016-01-26
申请号：US13571406
申请日：2012-08-10
申请人： Wei-Chuan Chen , Kangho Lee , Xiaochun Zhu , Seung H. Kang
发明人： Wei-Chuan Chen , Kangho Lee , Xiaochun Zhu , Seung H. Kang
IPC分类号： H01L43/08 , G11C11/16 , G11C11/15
CPC分类号： H01L43/02 , G11C11/15 , G11C11/16 , G11C11/161 , H01L43/08 , H01L43/10 , H01L43/12
摘要： Perpendicular magnetic anisotropy (PMA) type magnetic random access memory cells are constructed with a composite PMA layer to provide a magnetic tunnel junction (MTJ) with an acceptable thermal barrier. A PMA coupling layer is deposited between a first PMA layer and a second PMA layer to form the composite PMA layer. The composite PMA layer may be incorporated in PMA type MRAM cells or in-plane type MRAM cells.
摘要翻译：垂直磁各向异性（PMA）型磁性随机存取存储单元由复合PMA层构成，以提供具有可接受热障的磁隧道结（MTJ）。在第一PMA层和第二PMA层之间沉积PMA结合层以形成复合PMA层。复合PMA层可以并入PMA型MRAM细胞或平面内MRAM细胞中。

2. 发明授权

US09189201B2 Entropy source with magneto-resistive element for random number generator 有权
标题翻译：熵源与随机数发生器的磁阻元件
公开(公告)号：US09189201B2
公开(公告)日：2015-11-17
申请号：US13367322
申请日：2012-02-06
申请人： David M. Jacobson , Xiaochun Zhu , Wenqing Wu , Kendrick Hoy Leong Yuen , Seung H. Kang
发明人： David M. Jacobson , Xiaochun Zhu , Wenqing Wu , Kendrick Hoy Leong Yuen , Seung H. Kang
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , G06F5/01 , G06F2205/00 , G06F2207/581 , G11C11/1659 , G11C11/1673 , G11C11/1695 , G11C11/1697 , H03M7/30
摘要： An entropy source and a random number (RN) generator are disclosed. In one aspect, a low-energy entropy source includes a magneto-resistive (MR) element and a sensing circuit. The MR element is applied a static current and has a variable resistance determined based on magnetization of the MR element. The sensing circuit senses the resistance of the MR element and provides random values based on the sensed resistance of the MR element. In another aspect, a RN generator includes an entropy source and a post-processing module. The entropy source includes at least one MR element and provides first random values based on the at least one MR element. The post-processing module receives and processes the first random values (e.g., based on a cryptographic hash function, an error detection code, a stream cipher algorithm, etc.) and provides second random values having improved randomness characteristics.
摘要翻译：公开了熵源和随机数（RN）生成器。一方面，低能量熵源包括磁阻（MR）元件和感测电路。 MR元件施加静态电流，并具有基于MR元件的磁化确定的可变电阻。感测电路感测MR元件的电阻，并根据检测到的MR元件的电阻提供随机值。另一方面，RN发生器包括熵源和后处理模块。熵源包括至少一个MR元素，并且基于至少一个MR元素提供第一随机值。后处理模块接收并处理第一随机值（例如，基于加密散列函数，错误检测码，流密码算法等）并提供具有改进的随机特性的第二随机值。

3. 发明授权

US09159910B2 One-mask MTJ integration for STT MRAM 有权
标题翻译：用于STT MRAM的单掩模MTJ集成
公开(公告)号：US09159910B2
公开(公告)日：2015-10-13
申请号：US12355911
申请日：2009-01-19
申请人： Seung H. Kang , David Bang , Kangho Lee
发明人： Seung H. Kang , David Bang , Kangho Lee
IPC分类号： H01L21/00 , H01L43/12 , H01L43/08 , H01L27/22
CPC分类号： H01L43/02 , G11C11/16 , G11C11/161 , H01L27/228 , H01L43/08 , H01L43/12
摘要： A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first metal interconnect. Over the first interlevel dielectric layer and the first metal interconnect, magnetic tunnel junction material layers are deposited. From the material layers a magnetic tunnel junction stack, coupled to the first metal interconnect, is defined using a single mask process. The magnetic tunnel junction stack is integrated into the integrated circuit.
摘要翻译：将磁性隧道结（MTJ）器件集成到集成电路中的方法包括在半导体后端（BEOL）工艺流程中提供具有第一层间介电层和至少第一金属互连的衬底。在第一层间介电层和第一金属互连之后，沉积磁隧道结材料层。从材料层，使用单个掩模工艺来限定耦合到第一金属互连的磁性隧道结叠层。磁性隧道结堆叠集成在集成电路中。

4. 发明授权

US08693272B2 Sensing circuit 有权
标题翻译：感应电路
公开(公告)号：US08693272B2
公开(公告)日：2014-04-08
申请号：US13173641
申请日：2011-06-30
申请人： Seong-Ook Jung , Jisu Kim , Kyungho Ryu , Seung H. Kang
发明人： Seong-Ook Jung , Jisu Kim , Kyungho Ryu , Seung H. Kang
IPC分类号： G11C7/00
CPC分类号： G11C7/067 , G11C7/12 , G11C11/1655 , G11C11/1673 , G11C11/4091 , G11C13/004 , G11C16/26 , G11C2207/002
摘要： A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of an operational amplifier.
摘要翻译：电路包括退化的p沟道金属氧化物半导体（PMOS）晶体管，负载PMOS晶体管和钳位晶体管，其被配置为在感测操作期间钳位施加到基于电阻的存储元件的电压。负载PMOS晶体管的栅极由运算放大器的输出控制。

5. 发明申请

US20140050019A1 MULTI-LEVEL MEMORY CELL USING MULTIPLE MAGNETIC TUNNEL JUNCTIONS WITH VARYING MGO THICKNESS 有权
标题翻译：使用多个磁性隧道结的多级存储器单元与不同的MGO厚度
公开(公告)号：US20140050019A1
公开(公告)日：2014-02-20
申请号：US13589315
申请日：2012-08-20
申请人： Kangho Lee , Taehyun Kim , Jung Pill Kim , Seung H. Kang
发明人： Kangho Lee , Taehyun Kim , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/16 , H01L21/8239 , B05C11/00 , H01L43/12
CPC分类号： G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/5607 , H01L21/00
摘要： A Multi-Level Memory Cell (MLC) using multiple Magnetic Tunnel Junction (MTJ) structures having one or more layers with varying thickness is disclosed. The multiple MTJ structures, which are vertically stacked and arranged in series, may have substantially identical area dimensions to minimize fabrication costs because one mask can be used to pattern the multiple MTJ structures. Further, varying the thicknesses associated with the one or more layers may provide the multiple MTJ structures with different switching current densities and thereby increase memory density and improve read and write operations. In one embodiment, the layers with the varying thicknesses may include tunnel barriers or magnesium oxide layers associated with the multiple MTJ structures and/or free layers associated with the multiple MTJ structures.
摘要翻译：公开了使用具有一层或多层具有变化厚度的多个磁隧道结（MTJ）结构的多层存储单元（MLC）。垂直堆叠和串联布置的多个MTJ结构可以具有基本上相同的面积尺寸以最小化制造成本，因为可以使用一个掩模来对多个MTJ结构进行图案化。此外，改变与一个或多个层相关联的厚度可以为多个MTJ结构提供不同的开关电流密度，从而增加存储器密度并改善读取和写入操作。在一个实施例中，具有变化厚度的层可以包括与多个MTJ结构相关联的隧道势垒或氧化镁层，和/或与多个MTJ结构相关联的自由层。

6. 发明授权

US08625338B2 Asymmetric write scheme for magnetic bit cell elements 有权
标题翻译：磁位元件的非对称写入方案
公开(公告)号：US08625338B2
公开(公告)日：2014-01-07
申请号：US12755978
申请日：2010-04-07
申请人： Xiaochun Zhu , Hari M. Rao , Jung Pill Kim , Seung H. Kang
发明人： Xiaochun Zhu , Hari M. Rao , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/14
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1659 , G11C11/1693
摘要： Asymmetric switching is defined for magnetic bit cell elements. A magnetic bit cell for memory and other devices includes a transistor coupled to an MTJ structure. A bit line is coupled at one terminal of the bit cell to the MTJ structure. At another terminal of the bit cell, a source line is coupled to the source/drain terminal of the transistor. The bit line is driven by a bit line driver that provides a first voltage. The source line is driven by a source line driver that provides a second voltage. The second voltage is larger than the first voltage. The switching characteristics of the bit cell and MTJ structure are improved and made more reliable by one or a combination of applying the higher second voltage to the source line and/or reducing the overall parasitic resistance in the magnetic bit cell element.
摘要翻译：磁比特元件定义了非对称开关。用于存储器和其它器件的磁位单元包括耦合到MTJ结构的晶体管。位线在位单元的一个端子耦合到MTJ结构。在位单元的另一个端子处，源极线耦合到晶体管的源极/漏极端子。位线由提供第一电压的位线驱动器驱动。源极线由提供第二电压的源极线驱动器驱动。第二电压大于第一电压。通过将较高的第二电压施加到源极线和/或降低磁头单元元件中的整体寄生电阻的一个或组合来提高位单元和MTJ结构的开关特性并使其变得更可靠。

7. 发明授权

US08611132B2 Self-body biasing sensing circuit for resistance-based memories 有权
标题翻译：用于基于电阻的存储器的自身偏置感测电路
公开(公告)号：US08611132B2
公开(公告)日：2013-12-17
申请号：US13346029
申请日：2012-01-09
申请人： Seong-Ook Jung , Jisu Kim , Youngdon Jung , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Jisu Kim , Youngdon Jung , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C7/06 , G11C7/14 , G11C11/16 , G11C13/004 , G11C16/26 , G11C16/28
摘要： A resistance based memory sensing circuit has reference current transistors feeding a reference node and a read current transistor feeding a sense node, each transistor has a substrate body at a regular substrate voltage during a stand-by mode and biased during a sensing mode at a body bias voltage lower than the regular substrate voltage. In one option the body bias voltage is determined by a reference voltage on the reference node. The substrate body at the regular substrate voltage causes the transistors to have a regular threshold voltage, and the substrate body at the body bias voltage causes the transistors to have a sense mode threshold voltage, lower than the regular threshold voltage.
摘要翻译：基于电阻的存储器感测电路具有馈送参考节点的参考电流晶体管和馈送感测节点的读取电流晶体管，每个晶体管在待机模式期间具有处于规则衬底电压的衬底主体，并且在身体的感测模式期间被偏置偏置电压低于正常基板电压。在一个选项中，体偏置电压由参考节点上的参考电压确定。处于规则衬底电压的衬底体使晶体管具有规则的阈值电压，并且在体偏置电压下的衬底体使晶体管具有低于常规阈值电压的感测模式阈值电压。

8. 发明授权

US08536669B2 Magnetic element with storage layer materials 有权
标题翻译：磁性元件与存储层材料
公开(公告)号：US08536669B2
公开(公告)日：2013-09-17
申请号：US12352648
申请日：2009-01-13
申请人： Xiaochun Zhu , Xia Li , Seung H. Kang
发明人： Xiaochun Zhu , Xia Li , Seung H. Kang
IPC分类号： H01L29/82 , G11B5/33 , G11C11/02
CPC分类号： H01L43/10 , G11C11/161 , H01L43/12
摘要： According to an embodiment of the invention, a magnetic tunnel junction (MTJ) element includes a reference ferromagnetic layer, a storage ferromagnetic layer, and an insulating layer. The storage ferromagnetic layer includes a CoFeB sub-layer coupled to a CoFe sub-layer and/or a NiFe sub-layer through a non-magnetic sub-layer. The insulating layer is disposed between the reference and storage ferromagnetic layers.
摘要翻译：根据本发明的实施例，磁性隧道结（MTJ）元件包括参考铁磁层，存储铁磁层和绝缘层。存储铁磁层包括通过非磁性子层耦合到CoFe子层和/或NiFe子层的CoFeB子层。绝缘层设置在参考和存储铁磁层之间。

9. 发明授权

US08492858B2 Magnetic tunnel junction device and fabrication 有权
标题翻译：磁隧道连接装置及制造
公开(公告)号：US08492858B2
公开(公告)日：2013-07-23
申请号：US12548678
申请日：2009-08-27
申请人： Xia Li , Seung H. Kang
发明人： Xia Li , Seung H. Kang
IPC分类号： H01L29/82
CPC分类号： G06F17/50 , G11C11/161 , H01L43/08 , H01L43/12
摘要： A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming an MTJ cap layer on an MTJ structure and forming a top electrode layer over the MTJ cap layer. The top electrode layer includes a first nitrified metal.
摘要翻译：公开了一种磁性隧道结（MTJ）器件及其制造方法。在特定实施例中，形成磁性隧道结（MTJ）器件的方法包括在MTJ结构上形成MTJ覆盖层并在MTJ覆盖层上形成顶部电极层。顶部电极层包括第一硝化金属。

10. 发明授权

US08429577B2 Predictive modeling of interconnect modules for advanced on-chip interconnect technology 失效
标题翻译：用于先进片上互连技术的互连模块的预测建模
公开(公告)号：US08429577B2
公开(公告)日：2013-04-23
申请号：US12474297
申请日：2009-05-29
申请人： Xia Li , Wei Zhao , Yu Cao , Shiqun Gu , Seung H. Kang , Matthew Nowak
发明人： Xia Li , Wei Zhao , Yu Cao , Shiqun Gu , Seung H. Kang , Matthew Nowak
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5036
摘要： A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component.
摘要翻译：计算机程序产品估计半导体集成电路（IC）的互连结构的性能。程序产品包括在计算机上执行的代码，用于基于考虑到互连结构的多层的输入数据来计算互连结构的至少一个电特性。电气特性可以是电容，电阻和/或电感。电容可以基于多个分量，包括边缘电容分量，端子电容分量和耦合电容分量。

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