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    • 2. 发明授权
    • Apparatus and method for cross clock domain interference cancellation
    • 用于跨时钟域干扰消除的装置和方法
    • US08867650B2
    • 2014-10-21
    • US13396589
    • 2012-02-14
    • Liang-Wei HuangShieh-Hsing KuoChi-Shun WengChun-Hung Liu
    • Liang-Wei HuangShieh-Hsing KuoChi-Shun WengChun-Hung Liu
    • H04B15/00
    • H04L25/03019H04B1/525H04B15/02H04L2025/03617
    • An apparatus and method for cross clock domain interference cancellation is provided to a communication system which includes a transmitter operated in a first clock domain and a receiver operated in a second clock domain. The apparatus comprises a First-In-First-Out (FIFO) circuit and a cancellation signal generator. The FIFO circuit receives a digital transmission signal of the transmitter in the first clock domain, and outputs the digital transmission signal in the second clock domain according to an accumulated timing difference between the first and second clock domains. The cancellation signal generator generates a cancellation signal for canceling an interference signal received by the receiver according to the digital transmission signal outputted by the FIFO circuit. The interference signal is generated in response to the digital transmission signal. The cancellation signal generator adjusts the cancellation signal according to a phase difference between the interference signal and the cancellation signal.
    • 一种用于交叉时钟域干扰消除的装置和方法被提供给包括在第一时钟域中操作的发射机和在第二时钟域中操作的接收机的通信系统。 该装置包括先进先出(FIFO)电路和消除信号发生器。 FIFO电路在第一时钟域中接收发射机的数字传输信号,并根据第一和第二时钟域之间的累积时序差输出第二时钟域中的数字传输信号。 消除信号发生器根据由FIFO电路输出的数字传输信号产生消除由接收机接收的干扰信号的消除信号。 响应于数字传输信号产生干扰信号。 消除信号发生器根据干扰信号和消除信号之间的相位差来调整抵消信号。
    • 4. 发明申请
    • APPARATUS AND METHOD FOR CROSS CLOCK DOMAIN INTERFERENCE CANCELLATION
    • 用于跨时间域干扰消除的装置和方法
    • US20120213306A1
    • 2012-08-23
    • US13396589
    • 2012-02-14
    • Liang-Wei HuangShieh-Hsing KuoChi-Shun WengChun-Hung Liu
    • Liang-Wei HuangShieh-Hsing KuoChi-Shun WengChun-Hung Liu
    • H04B15/00
    • H04L25/03019H04B1/525H04B15/02H04L2025/03617
    • An apparatus and method for cross clock domain interference cancellation is provided to a communication system which includes a transmitter operated in a first clock domain and a receiver operated in a second clock domain. The apparatus comprises a First-In-First-Out (FIFO) circuit and a cancellation signal generator. The FIFO circuit receives a digital transmission signal of the transmitter in the first clock domain, and outputs the digital transmission signal in the second clock domain according to an accumulated timing difference between the first and second clock domains. The cancellation signal generator generates a cancellation signal for canceling an interference signal received by the receiver according to the digital transmission signal outputted by the FIFO circuit. The interference signal is generated in response to the digital transmission signal. The cancellation signal generator adjusts the cancellation signal according to a phase difference between the interference signal and the cancellation signal.
    • 一种用于交叉时钟域干扰消除的装置和方法被提供给包括在第一时钟域中操作的发射机和在第二时钟域中操作的接收机的通信系统。 该装置包括先进先出(FIFO)电路和消除信号发生器。 FIFO电路在第一时钟域中接收发射机的数字传输信号,并根据第一和第二时钟域之间的累积时序差输出第二时钟域中的数字传输信号。 消除信号发生器根据由FIFO电路输出的数字传输信号产生消除由接收机接收的干扰信号的消除信号。 响应于数字传输信号产生干扰信号。 消除信号发生器根据干扰信号和消除信号之间的相位差来调整抵消信号。
    • 9. 发明授权
    • Transceiver with adjustable sampling values and signal transceiving method thereof
    • 收发器具有可调取样值及其信号收发方法
    • US08165188B2
    • 2012-04-24
    • US12346897
    • 2008-12-31
    • Chih-Yung ShihLiang-Wei HuangShieh-Hsing KuoChi-Shun Weng
    • Chih-Yung ShihLiang-Wei HuangShieh-Hsing KuoChi-Shun Weng
    • H04L5/16
    • H04L7/033H03L7/0812H04B3/23H04L7/0087
    • A transceiver includes: a first DAC, for receiving a first digital signal to generate an analog signal; an operation circuit, coupled to the first DAC, for receiving the analog signal and a feedback signal to generate an operated analog signal; an ADC, for generating a second digital signal according to the operated analog signal; a digital signal processing circuit, for processing the second digital signal to generate a processed digital signal; a second DAC, for generating the feedback signal according to the processed digital signal; an adjustable delay circuit, for delaying a clock signal according to a control signal to adjust at least one sampling point of at least one of the first DAC, the second DAC and the ADC; and a control circuit, for generating the control signal according to the processed digital signal.
    • 收发器包括:第一DAC,用于接收第一数字信号以产生模拟信号; 耦合到第一DAC的操作电路,用于接收模拟信号和反馈信号以产生操作的模拟信号; ADC,用于根据所操作的模拟信号产生第二数字信号; 数字信号处理电路,用于处理第二数字信号以产生经处理的数字信号; 第二DAC,用于根据所处理的数字信号产生反馈信号; 可调延迟电路,用于根据控制信号延迟时钟信号以调整第一DAC,第二DAC和ADC中的至少一个的至少一个采样点; 以及控制电路,用于根据处理的数字信号产生控制信号。