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1. 发明授权

US08144072B2 Multi-band antenna for notebook computer 有权
标题翻译：笔记本电脑多频天线
公开(公告)号：US08144072B2
公开(公告)日：2012-03-27
申请号：US12535605
申请日：2009-08-04
申请人： Chi-Ming Chiang , Daniel Chang , Shih-Chi Lai
发明人： Chi-Ming Chiang , Daniel Chang , Shih-Chi Lai
IPC分类号： H01Q1/24 , H01Q1/38
CPC分类号： H01Q9/42 , H01Q1/2266 , H01Q5/321
摘要： A multi-band antenna includes an insulative carrier board arranged on the top side of the display screen of a notebook computer, a main antenna which has the top metal strip thereof disposed at the top edge of the insulative carrier board and the grounding metal strip thereon arranged on the insulative carrier board, an inverted L antenna arranged on the insulative carrier board, a first capacitor, a second capacitor, an antenna feed-in terminal and/or an inductor set between the inverted L antenna and the main antenna to achieve optimal matching subject to adjustment of the capacitance values of the first and second capacitors and the inductance value and position of the inductor.
摘要翻译：多频带天线包括布置在笔记本电脑的显示屏的顶侧上的绝缘载板，主天线，其顶顶金属带设置在绝缘载板的顶边缘和接地金属条上，布置在绝缘载板上，布置在绝缘载板上的倒置L天线，设置在倒置L天线和主天线之间的第一电容器，第二电容器，天线馈入端子和/或电感器，以实现最佳匹配受到第一和第二电容器的电容值的调整以及电感器的电感值和位置。

2. 发明申请

US20110032170A1 MULTI-BAND ANTENNA FOR NOTEBOOK COMPUTER 有权
标题翻译：笔记本电脑的多天线
公开(公告)号：US20110032170A1
公开(公告)日：2011-02-10
申请号：US12535605
申请日：2009-08-04
申请人： Chi-Ming CHIANG , Daniel CHANG , Shih-Chi LAI
发明人： Chi-Ming CHIANG , Daniel CHANG , Shih-Chi LAI
IPC分类号： H01Q1/38 , H01Q1/50
CPC分类号： H01Q9/42 , H01Q1/2266 , H01Q5/321
摘要： A multi-band antenna includes an insulative carrier board arranged on the top side of the display screen of a notebook computer, a main antenna which has the top metal strip thereof disposed at the top edge of the insulative carrier board and the grounding metal strip thereon arranged on the insulative carrier board, an inverted L antenna arranged on the insulative carrier board, a first capacitor, a second capacitor, an antenna feed-in terminal and/or an inductor set between the inverted L antenna and the main antenna to achieve optimal matching subject to adjustment of the capacitance values of the first and second capacitors and the inductance value and position of the inductor.
摘要翻译：多频带天线包括布置在笔记本电脑的显示屏的顶侧上的绝缘载板，主天线，其顶顶金属带设置在绝缘载板的顶边缘和接地金属条上，布置在绝缘载板上，布置在绝缘载板上的倒置L天线，设置在倒置L天线和主天线之间的第一电容器，第二电容器，天线馈入端子和/或电感器，以实现最佳匹配受到第一和第二电容器的电容值的调整以及电感器的电感值和位置。

3. 发明申请

US20080280430A1 METHOD OF FORMING FILMS IN A TRENCH 审中-公开
标题翻译：在TRENCH中形成膜的方法
公开(公告)号：US20080280430A1
公开(公告)日：2008-11-13
申请号：US12120885
申请日：2008-05-15
申请人： Shih-Chi Lai , Tun-Fu Hung , Yi-Fu Chung , Jen-Chieh Chang
发明人： Shih-Chi Lai , Tun-Fu Hung , Yi-Fu Chung , Jen-Chieh Chang
IPC分类号： H01L21/283
CPC分类号： H01L29/513 , H01L21/31053 , H01L21/31662 , H01L21/3185 , H01L29/66734
摘要： A method of forming films in a trench is applied to the manufacturing process of a power MOS device. In one embodiment, the method comprises providing a semiconductor substrate, forming a trench in the semiconductor substrate, forming a first dielectric layer on sidewalls of the trench, forming a second dielectric layer on the first dielectric layer, and forming a polysilicon layer in the trench. The method of forming films in a trench of the present invention can reduce or eliminate the thermal stress resulting from the different thermal expansion coefficients of different material layers after high temperature process.
摘要翻译：在沟槽中形成膜的方法被应用于功率MOS器件的制造过程。在一个实施例中，该方法包括提供半导体衬底，在半导体衬底中形成沟槽，在沟槽的侧壁上形成第一电介质层，在第一电介质层上形成第二电介质层，以及在沟槽中形成多晶硅层。在本发明的沟槽中形成膜的方法可以降低或消除由高温处理后的不同材料层的不同热膨胀系数产生的热应力。

4. 发明授权

US07015112B2 Method of forming bottom oxide layer in trench structure 有权
标题翻译：在沟槽结构中形成底部氧化物层的方法
公开(公告)号：US07015112B2
公开(公告)日：2006-03-21
申请号：US10668454
申请日：2003-09-22
申请人： Ta-Chung Wu , Yi-Chuan Yang , Shih-Chi Lai , Yew-Jung Chang
发明人： Ta-Chung Wu , Yi-Chuan Yang , Shih-Chi Lai , Yew-Jung Chang
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L29/42368 , H01L29/7813
摘要： Embodiments of the invention are directed to a method of forming a bottom oxide in a trench structure. In one embodiment, the method includes steps of providing a semiconductor substrate and forming a trench structure in the semiconductor substrate; performing an PECVD process with TEOS as a source to deposit an oxide layer on the bottom and sidewall of the trench structure and the semiconductor substrate; and removing the oxide layer on the sidewall of the trench structure substantially completely and the oxide layer on the bottom of the trench structure partially to define the remained oxide layer as the bottom oxide layer.
摘要翻译：本发明的实施例涉及在沟槽结构中形成底部氧化物的方法。在一个实施例中，该方法包括以下步骤：提供半导体衬底并在半导体衬底中形成沟槽结构; 以TEOS作为源进行PECVD处理，以在沟槽结构和半导体衬底的底部和侧壁上沉积氧化物层; 并且基本上完全去除沟槽结构的侧壁上的氧化物层，并且部分地去除沟槽结构的底部上的氧化物层以限定作为底部氧化物层的剩余氧化物层。

5. 发明授权

US06974749B2 Bottom oxide formation process for preventing formation of voids in trench 有权
标题翻译：用于防止在沟槽中形成空隙的底部氧化物形成工艺
公开(公告)号：US06974749B2
公开(公告)日：2005-12-13
申请号：US10677568
申请日：2003-10-01
申请人： Shih-Chi Lai , Yifu Chung , Yi-Chuan Yang , Jen-Chieh Chang , Jason Chien-Sung Chu , Chun-De Lin
发明人： Shih-Chi Lai , Yifu Chung , Yi-Chuan Yang , Jen-Chieh Chang , Jason Chien-Sung Chu , Chun-De Lin
IPC分类号： H01L21/762 , H01L21/763 , H01L21/336
CPC分类号： H01L21/763 , H01L21/76224 , H01L29/42368 , H01L29/66734
摘要： Embodiments of the present invention are directed to a method of forming a bottom oxide layer in the trench in semiconductor devices, such as Double-Diffused Metal-Oxide Semiconductor (DMOS) devices. In one embodiment, a method of forming a bottom oxide layer in a trench structure comprises providing a semiconductor substrate; forming a silicon nitride layer on the semiconductor substrate; forming a first oxide layer on the silicon nitride layer; forming a trench structure in the semiconductor substrate; forming a second oxide layer on a bottom and sidewalls of the trench and on a surface of the first oxide layer; removing the first oxide layer and the second oxide layer on the surface of the silicon nitride layer; and removing the second oxide layer on the sidewalls of the trench and a portion of the second oxide layer on the bottom of the trench.
摘要翻译：本发明的实施例涉及在诸如双扩散金属氧化物半导体（DMOS）器件的半导体器件中的沟槽中形成底部氧化物层的方法。在一个实施例中，在沟槽结构中形成底部氧化物层的方法包括提供半导体衬底; 在所述半导体衬底上形成氮化硅层; 在所述氮化硅层上形成第一氧化物层; 在所述半导体衬底中形成沟槽结构; 在所述沟槽的底部和侧壁上以及所述第一氧化物层的表面上形成第二氧化物层; 去除氮化硅层表面上的第一氧化物层和第二氧化物层; 并且去除沟槽的侧壁上的第二氧化物层和沟槽底部上的第二氧化物层的一部分。

6. 发明授权

US06374833B1 Method of in situ reactive gas plasma treatment 有权
标题翻译：原位反应气体等离子体处理方法
公开(公告)号：US06374833B1
公开(公告)日：2002-04-23
申请号：US09305524
申请日：1999-05-05
申请人： Tien-Min Yuan , Shih-Chi Lai , Yen-Chung Feng , Tsung-Hua Wu
发明人： Tien-Min Yuan , Shih-Chi Lai , Yen-Chung Feng , Tsung-Hua Wu
IPC分类号： C25F100
CPC分类号： H01J37/32844 , H01J37/3244 , H01L21/32136 , Y02C20/30 , Y02P70/605 , Y10S134/902 , Y10S438/905 , Y10S438/906
摘要： A method of in situ reactive gas plasma treatment is disclosed. The method is capable of removing a residue remained in a metal etching chamber after the metal etching process to improve the yield of the wafer and the particle performance of the metal etching chamber. The method includes the steps of (a) vactuating the metal etching chamber after the metal etching process, (b) introducing a reactive gas to the metal etching chamber, and (c) applying an electromagnetic power to the metal etching chamber for producing a plasma derived from the reactive gas to remove the residue inside the metal etching chamber and/or on the wafer.
摘要翻译：公开了一种原位反应气体等离子体处理方法。该方法能够在金属蚀刻工艺之后除去残留在金属蚀刻室中的残留物，以提高晶片的产率和金属蚀刻室的颗粒性能。该方法包括以下步骤：（a）在金属蚀刻工艺之后对金属蚀刻室进行制作，（b）向金属蚀刻室引入反应性气体，和（c）向金属蚀刻室施加电磁功率以产生等离子体衍生自反应性气体以除去金属蚀刻室内和/或晶片上的残余物。

7. 发明授权

US08542152B2 Multi-band antenna 有权
标题翻译：多频天线
公开(公告)号：US08542152B2
公开(公告)日：2013-09-24
申请号：US13004253
申请日：2011-01-11
申请人： Chih-Yin Yu , Shih-Chi Lai , Chia-Lun Tang , Jia-Yi Sze
发明人： Chih-Yin Yu , Shih-Chi Lai , Chia-Lun Tang , Jia-Yi Sze
IPC分类号： H01Q1/38 , H01Q1/24
CPC分类号： H01Q9/0471 , H01Q1/243 , H01Q5/357 , H01Q9/42
摘要： A multi-frequency antenna includes a microwave substrate, a first antenna unit, a second antenna unit, a third antenna unit and a grounding unit. The first antenna unit, the second antenna unit, and the third antenna unit are disposed on the microwave substrate surface. The grounding unit is disposed at an edge on the surface of the microwave substrate. The grounding unit is in connection with the second antenna unit. The second antenna unit and the third antenna unit are bent to form perpendicular structures to the microwave substrate. The compact arrangement reduces the physical footprint of the antenna module to enable fitment in a wide range of products having tight special constraint.
摘要翻译：多频天线包括微波基板，第一天线单元，第二天线单元，第三天线单元和接地单元。第一天线单元，第二天线单元和第三天线单元设置在微波基板表面上。接地单元设置在微波基板表面的边缘。接地单元与第二天线单元连接。第二天线单元和第三天线单元被弯曲以形成与微波基板的垂直结构。紧凑的布置减少了天线模块的物理尺寸，使得能够在具有紧密特殊约束的宽范围的产品中进行装配。

8. 发明申请

US20110037678A1 MULTIFUNCTIONAL ANTENNA CHIP 有权
标题翻译：多功能天线芯片
公开(公告)号：US20110037678A1
公开(公告)日：2011-02-17
申请号：US12542093
申请日：2009-08-17
申请人： Chia-Lun TANG , Shih-Chi Lai
发明人： Chia-Lun TANG , Shih-Chi Lai
IPC分类号： H01Q1/38 , H01Q1/50
CPC分类号： H01Q1/2283 , H01Q1/2266 , H01Q1/36 , H01Q9/0421
摘要： A multifunctional antenna chip is able to mate with many kinds of matched circuits and is able to adjust the character of an antenna structure of the multifunctional antenna chip, in order that the antenna structure has one or multiple standard working frequencies. The antenna structure is a folded antenna structure basically; this can save its volume occupied. And the multifunctional antenna chip has a non-signal inputting pin for connection to thereby increase shape of the antenna for adjusting the style of the antenna structure designed.
摘要翻译：多功能天线芯片能够与多种匹配电路配合，并且能够调整多功能天线芯片的天线结构的特性，以便天线结构具有一个或多个标准工作频率。天线结构基本上是折叠天线结构; 这可以节省其占用量。并且多功能天线芯片具有用于连接的非信号输入引脚，从而增加天线的形状，以调整设计的天线结构的风格。

9. 发明授权

US07282429B2 Method of manufacturing Schottky diode device 有权
标题翻译：制造肖特基二极管器件的方法
公开(公告)号：US07282429B2
公开(公告)日：2007-10-16
申请号：US11208374
申请日：2005-08-19
申请人： Shih-Chi Lai , Pei-Feng Sun , Yi Fu Chung , Jen Chieh Chang
发明人： Shih-Chi Lai , Pei-Feng Sun , Yi Fu Chung , Jen Chieh Chang
IPC分类号： H01L21/28
CPC分类号： H01L29/66143 , H01L21/32105 , H01L21/32139 , H01L27/0814
摘要： Embodiments of the invention provide a method of manufacturing a Schottky diode device. In one embodiment, the method includes: (a) providing a substrate; (b) sequentially forming a gate oxide layer and a polysilicon layer on the substrate; (c) partially oxidizing the polysilicon layer to form a poly oxide layer on the polysilicon layer; (d) forming and defining a photoresist layer on the poly oxide layer for exposing parts of the poly oxide layer; (e) etching the poly oxide layer, the polysilicon layer and the gate oxide layer via the photoresist layer for forming a poly oxide structure, a polysilicon structure and a gate oxide structure; and (f) removing the photoresist layer. The present invention introduces a poly oxide layer instead of the CVD oxide for preventing the photoresist lifting issue.
摘要翻译：本发明的实施例提供一种制造肖特基二极管器件的方法。在一个实施例中，该方法包括：（a）提供衬底; （b）在基板上依次形成栅氧化层和多晶硅层; （c）在所述多晶硅层上部分氧化所述多晶硅层以形成多晶氧化物层; （d）在所述多晶氧化物层上形成和限定光致抗蚀剂层，以暴露所述多晶氧化物层的部分; （e）经由用于形成多晶氧化物结构的光致抗蚀剂层，多晶硅结构和栅极氧化物结构蚀刻多晶氧化物层，多晶硅层和栅极氧化物层; 和（f）去除光致抗蚀剂层。本发明引入了用于防止光致抗蚀剂提升问题的多氧化物层代替CVD氧化物。

10. 发明授权

US06403489B1 Method for removing polymer stacked on a lower electrode within an etching reaction chamber 失效
标题翻译：在蚀刻反应室内去除堆叠在下电极上的聚合物的方法
公开(公告)号：US06403489B1
公开(公告)日：2002-06-11
申请号：US09598838
申请日：2000-06-21
申请人： Tien-min Yuan , Kuang-yung Wu , Shih-chi Lai , Kuo-tsai Kao
发明人： Tien-min Yuan , Kuang-yung Wu , Shih-chi Lai , Kuo-tsai Kao
IPC分类号： H01L21302
CPC分类号： H01J37/32862
摘要： An object of the invention is to provide a preventive maintenance for effectively removing polymer stacked on a lower electrode within a reaction chamber of etching equipment during the process of dry etching of a silicon oxide layer. First, the lower electrode is preferably set at 0° C., and then the reaction chamber is pre-cleaned preferably 20 times by a pump/purge cleaning manner. After the pre-cleaning, nitrogen or inert gas is supplied into the reaction chamber such that the internal pressure is equal to atmospheric pressure. Subsequently, the reaction chamber is opened preferably for 10 minutes, and the lower electrode is kept at 0° C. during this moment. Afterwards, the surface of the lower electrode is wiped by a piece of clean cloth to peel off the polymer. Finally, the lower electrode is preferably set at 25° C. and is wiped several times by using de-ionized water, isopropanol (IPA), ethanol, a solution of hydrogen peroxide in water, or Cleaner 5060 produced by the 3M corporation. According to the invention, the surface of the lower electrode does not suffer scratches and damage caused by a scraper. Therefore, the lifespan of the lower electrode is increased and the stability of the etching process is successfully enhanced.
摘要翻译：本发明的目的是提供一种在氧化硅层的干蚀刻过程中有效去除在蚀刻设备的反应室内堆叠在下电极上的聚合物的预防性维护。首先，将下电极优选设定为0℃，然后通过泵/清洗方式将反应室预先清洗20次。在预清洁之后，将氮气或惰性气体供应到反应室中，使得内部压力等于大气压力。随后，反应室优选打开10分钟，此时下电极保持在0℃。然后，用一块干净的布擦拭下电极的表面以剥离聚合物。最后，下电极优选设定在25℃，并使用去离子水，异丙醇（IPA），乙醇，水中的过氧化氢溶液或由3M公司生产的Cleaner 5060擦拭数次。根据本发明，下电极的表面不会受到划痕和由刮刀造成的损坏。因此，下电极的寿命增加，并且蚀刻工艺的稳定性被成功地提高。

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