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1. 发明授权

US08773141B2 Test apparatus and circuit module 有权
标题翻译：测试仪器和电路模块
公开(公告)号：US08773141B2
公开(公告)日：2014-07-08
申请号：US13082386
申请日：2011-04-07
申请人： Tsuyoshi Ataka , Shoji Kojima
发明人： Tsuyoshi Ataka , Shoji Kojima
IPC分类号： G01R31/02
CPC分类号： G01R31/2874
摘要： Provided are a first test substrate and a second test substrate opposing each other, a first test circuit testing a device under test and being disposed on a face of the first test substrate that faces the second test substrate, a second test circuit testing the device under test and being disposed on a face of the second test substrate that faces the first test substrate, and a sealing section that is formed by sealing a space between the first test substrate and the second test substrate to enclose the first test circuit and the second test circuit in a common space that is filled with coolant.
摘要翻译：提供了第一测试基板和第二测试基板，第一测试电路测试被测器件并且设置在面向第二测试基板的第一测试基板的表面上，第二测试电路测试该器件的第二测试电路测试并设置在面对第一测试基板的第二测试基板的表面上，以及密封部分，其通过密封第一测试基板和第二测试基板之间的空间来封装第一测试电路和第二测试电路在充满冷却剂的公共空间中。

2. 发明授权

US08575961B2 Multi-valued driver circuit 失效
标题翻译：多值驱动电路
公开(公告)号：US08575961B2
公开(公告)日：2013-11-05
申请号：US13501451
申请日：2009-10-13
申请人： Shoji Kojima
发明人： Shoji Kojima
IPC分类号： H03K19/00 , H04L27/04
CPC分类号： H04L25/0272 , H04L25/4917
摘要： A multi-valued driver circuit selectively outputs, to a transmission line, one from among multiple voltages according to a selection signal. A memory circuit stores setting data which define the respective levels of the multiple voltages. According to the selection signal, a selector circuit selects one from among the multiple setting data stored in the memory circuit. A Thevenin termination circuit outputs a voltage that corresponds to the upper M bits of the data thus selected by the selector circuit. An R-2R ladder circuit outputs a voltage that corresponds to the lower Nl bits of the data thus selected by the selector circuit.
摘要翻译：多值驱动器电路根据选择信号选择性地向传输线输出多个电压中的一个。存储电路存储定义多个电压的各个电平的设置数据。根据选择信号，选择器电路从存储在存储电路中的多个设置数据中选择一个。戴维宁终端电路输出与由选择器电路所选择的数据的高M位对应的电压。 R-2R梯形电路输出对应于由选择器电路所选择的数据的低Nl位的电压。

3. 发明申请

US20120194374A1 DIGITAL TO ANALOG CONVERTER 失效
标题翻译：数字到模拟转换器
公开(公告)号：US20120194374A1
公开(公告)日：2012-08-02
申请号：US13360610
申请日：2012-01-27
申请人： Ken'ichi Sawada , Shoji KOJIMA
发明人： Ken'ichi Sawada , Shoji KOJIMA
IPC分类号： H03M1/66
CPC分类号： H03M1/068 , H03M1/808
摘要： N upper-side resistors and N lower-side resistors are severally associated with respective bits of a digital input code. Each resistance value is weighted in an essentially binary manner according to the corresponding bit. N upper-side switches are each arranged in parallel with a corresponding upper-side resistor, and each is configured such that its on/off state is controlled according to the corresponding bit. N lower-side switches are each arranged in parallel with a corresponding lower-side resistor, and each is configured such that its on/off state is controlled according to logical inversion of the corresponding bit.
摘要翻译： N个上侧电阻器和N个下侧电阻器分别与数字输入代码的各个位相关联。每个电阻值根据相应的位以基本上二进制的方式进行加权。 N个上侧开关各自与相应的上侧电阻并联布置，并且每个被配置为使得其根据相应位的控制。 N个下侧开关各自与相应的下侧电阻器并联布置，并且每个被配置为使得其根据相应位的逻辑反相来控制其导通/截止状态。

4. 发明授权

US08220947B2 Differential driver circuit 失效
标题翻译：差分驱动电路
公开(公告)号：US08220947B2
公开(公告)日：2012-07-17
申请号：US13002975
申请日：2009-10-14
申请人： Yasuyuki Arai , Shoji Kojima
发明人： Yasuyuki Arai , Shoji Kojima
IPC分类号： H03K19/086
CPC分类号： H03G1/0088 , G01R31/31706 , H03F3/45183 , H03F3/72 , H03F2203/45358
摘要： A first current source supplies a tail current It to a plurality of differential pairs. A pre-driver outputs gate signals to the gates of transistors of the corresponding differential pair. A pre-driver is configured to switch the state between the enable state and the disable state. In the enable state, the pre-driver outputs the gate signals that correspond to the differential signals. In the disable state, the pre-driver outputs the gate signals having levels which instruct the transistors of the corresponding differential pair to switch off.
摘要翻译：第一电流源将尾电流It提供给多个差分对。预驱动器将门信号输出到相应差分对的晶体管的栅极。预驱动器被配置为在使能状态和禁止状态之间切换状态。在使能状态下，预驱动器输出与差分信号对应的门信号。在禁止状态下，预驱动器输出具有指示相应差分对的晶体管关断的电平的门信号。

5. 发明申请

US20120161840A1 SR FLIP-FLOP 失效
公开(公告)号：US20120161840A1
公开(公告)日：2012-06-28
申请号：US13335458
申请日：2011-12-22
申请人： Shoji Kojima
发明人： Shoji Kojima
IPC分类号： H03K3/037 , H03K12/00
CPC分类号： H03K3/0375
摘要： An input priority determination circuit is configured such that: (i) when a set signal S is asserted and a reset signal R is negated, an intermediate set signal S′ is asserted and an intermediate reset signal R′ is negated; (ii) when the set signal S is negated and the reset signal R is asserted, the intermediate set signal S′ is negated, and the intermediate reset signal R′ is asserted; (iii) when a control signal P indicates a set priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S′ is asserted and the intermediate reset signal R′ is negated; and (iv) when the control signal P indicates a reset priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S′ is negated and the intermediate reset signal R′ is asserted.
摘要翻译：输入优先级确定电路被配置为使得：（i）当置位信号S被确定并且复位信号R被否定时，中断设置信号S'被断言并且中间复位信号R'被否定; （ii）当设定信号S被否定并且复位信号R被断言时，中间设置信号S'被否定，并且中断复位信号R'被断言; （iii）当控制信号P指示设定的优先模式时，并且当设定信号S和复位信号R均被断言时，中间设定信号S'被置位，中间复位信号R'被否定; 和（iv）当控制信号P指示复位优先模式时，并且当设置信号S和复位信号R均被断言时，中间设置信号S'被否定，并且中间复位信号R'被断言。

6. 发明申请

US20120119752A1 TEST APPARATUS AND CIRCUIT MODULE 有权
标题翻译：测试装置和电路模块
公开(公告)号：US20120119752A1
公开(公告)日：2012-05-17
申请号：US13082386
申请日：2011-04-07
申请人： Tsuyoshi Ataka , Shoji Kojima
发明人： Tsuyoshi Ataka , Shoji Kojima
IPC分类号： G01R31/02
CPC分类号： G01R31/2874
摘要： Provided are a first test substrate and a second test substrate opposing each other, a first test circuit testing a device under test and being disposed on a face of the first test substrate that faces the second test substrate, a second test circuit testing the device under test and being disposed on a face of the second test substrate that faces the first test substrate, and a sealing section that is formed by sealing a space between the first test substrate and the second test substrate to enclose the first test circuit and the second test circuit in a common space that is filled with coolant.
摘要翻译：提供了第一测试基板和第二测试基板，第一测试电路测试被测器件并设置在面对第二测试基板的第一测试基板的表面上，第二测试电路测试该器件的第二测试电路测试并设置在面对第一测试基板的第二测试基板的表面上，以及密封部分，其通过密封第一测试基板和第二测试基板之间的空间来封装第一测试电路和第二测试电路在充满冷却剂的公共空间中。

7. 发明授权

US07952359B2 Test apparatus having bidirectional differential interface 有权
标题翻译：具有双向差分接口的测试设备
公开(公告)号：US07952359B2
公开(公告)日：2011-05-31
申请号：US12390292
申请日：2009-02-20
申请人： Shoji Kojima
发明人： Shoji Kojima
IPC分类号： G01R31/08
CPC分类号： G01R31/31924 , G01R31/31706 , G01R31/31905 , G01R31/31926
摘要： First and second resistors are provided between a first input/output terminal and a power supply terminal, and between a second input/output terminal and the power supply terminal, respectively. Third and fourth resistors are connected to the second and first input/output terminals, respectively. First and second current-switching switches couple either the first input/output terminal side or the second input/output terminal side with a first current source and a second current source, respectively, according to the value of pattern data. A level shift circuit shifts the electric potentials at the second terminals of the third and forth resistors by a predetermined level. A comparator circuit compares the electric potentials at the second terminals of the third and fourth resistors level-shifted by the level shift circuit with those at the second terminals of the fourth and third resistors, respectively, and generates first and second comparison signals according to the comparison results.
摘要翻译：第一和第二电阻器分别设置在第一输入/输出端子和电源端子之间，以及第二输入/输出端子与电源端子之间。第三和第四电阻器分别连接到第二和第一输入/输出端子。第一和第二电流切换开关根据图案数据的值分别将第一输入/输出端子侧或第二输入/输出端子侧分别与第一电流源和第二电流源耦合。电平移位电路将第三和第四电阻器的第二端子处的电位移动预定电平。比较器电路将电平移位电路电平移位的第三和第四电阻器的第二端子处的电位与第四和第三电阻器的第二端子处的电位进行比较，并根据第二和第二比较信号产生第一和第二比较信号比较结果。

8. 发明申请

US20100148826A1 DIFFERENTIAL COMPARATOR WITH SKEW COMPENSATION FUNCTION AND TEST APPARATUS USING THE SAME 有权
标题翻译：具有补偿功能的差分比较器和使用其的测试装置
公开(公告)号：US20100148826A1
公开(公告)日：2010-06-17
申请号：US12337566
申请日：2008-12-17
申请人： Shoji Kojima
发明人： Shoji Kojima
IPC分类号： H03K5/22 , G01D1/14
CPC分类号： H03K5/08 , G01R31/2889 , H03K5/2481
摘要： One of differential signals is inputted to a first input terminal. The other of the differential signals is inputted to a second input terminal. A first sample hold circuit samples the signal inputted to the first input terminal and hold it thereafter. A second sample hold circuit samples the signal inputted to the second input terminal and holds it thereafter. A comparison unit compares a signal corresponding to a difference between respective output signals from the first and the second sample hold circuits, with a predetermined threshold value. A latch circuit latches an output from the comparison unit. Sample timings of the first and the second sample hold circuits and a latch timing of the latch circuit can be adjusted independently.
摘要翻译：一个差分信号被输入到第一输入端。差分信号中的另一个被输入到第二输入端。第一采样保持电路对输入到第一输入端的信号进行采样，然后保持。第二采样保持电路对输入到第二输入端的信号进行采样，然后保持。比较单元将与来自第一和第二采样保持电路的各个输出信号之间的差相对应的信号与预定阈值进行比较。锁存电路锁存比较单元的输出。可以独立地调整第一和第二采样保持电路的采样定时和锁存电路的锁存定时。

9. 发明申请

US20090273384A1 VERNIER DELAY CIRCUIT 有权
标题翻译： VERNIER DELAY电路
公开(公告)号：US20090273384A1
公开(公告)日：2009-11-05
申请号：US12396219
申请日：2009-03-02
申请人： Shoji Kojima , Masakatsu Suda
发明人： Shoji Kojima , Masakatsu Suda
IPC分类号： H03H11/26
CPC分类号： H03K5/131 , H03K2005/00052 , H03K2005/00065 , H03L7/0805 , H03L7/0995
摘要： A ring oscillator oscillates at a frequency determined by an input bias signal. A bias signal adjusting unit produces a bias signal for the ring oscillator using feedback so that the oscillation frequency of the ring oscillator matches a predetermined reference frequency. An individual bias circuit includes a plurality of bias circuits provided for a total of N second variable delay elements, respectively. The bias circuits are configured such that the bias signals can be individually adjusted.
摘要翻译：环形振荡器以由输入偏置信号确定的频率振荡。偏置信号调整单元使用反馈产生环形振荡器的偏置信号，使得环形振荡器的振荡频率与预定的参考频率匹配。单独的偏置电路包括分别为总共N个第二可变延迟元件提供的多个偏置电路。偏置电路被配置成使得可以单独地调整偏置信号。

10. 发明申请

US20090251001A1 SEMICONDUCTOR CIRCUIT 失效
标题翻译：半导体电路
公开(公告)号：US20090251001A1
公开(公告)日：2009-10-08
申请号：US12410098
申请日：2009-03-24
申请人： Shoji Kojima , Toshiyuki Okayasu
发明人： Shoji Kojima , Toshiyuki Okayasu
IPC分类号： H02J4/00
CPC分类号： H03F1/0211 , H03F2200/516 , H03K19/00369 , Y10T307/305
摘要： A first signal processing circuit performs predetermined signal processing on a first signal to provide a change to a characteristic value thereof, and then outputs a second signal. A second signal processing circuit performs predetermined signal processing on the second signal to provide a change to a characteristic value thereof, and then outputs a third signal. A first and a second switching power supplies respectively supply power supply voltages to the first and second signal processing circuits. An amount of change provided to the characteristic value of the first signal by the first signal processing circuit, and an amount of change provided to the characteristic value of the second signal by the second signal processing circuit, are dependent on the respective power supply voltages. Phases of the first and the second switching power supplies are respectively set such that an error between the amount of change in the characteristic value of the first signal and its target value, and an error between that of the second signal and its target value, are to be canceled out by each other.
摘要翻译：第一信号处理电路对第一信号执行预定的信号处理以对其特征值进行改变，然后输出第二信号。第二信号处理电路对第二信号执行预定的信号处理以提供对其特征值的改变，然后输出第三信号。第一和第二开关电源分别向第一和第二信号处理电路提供电源电压。由第一信号处理电路提供给第一信号的特性值的改变量以及由第二信号处理电路提供给第二信号的特性值的变化量取决于相应的电源电压。分别设定第一和第二开关电源的相位，使得第一信号的特性值的变化量与其目标值之间的误差以及第二信号的特性值的变化量与其目标值之间的误差为被彼此取消。

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