专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08269346B2 Semiconductor device and method of designing a wiring of a semiconductor device 有权
标题翻译：半导体装置及其设计方法
公开(公告)号：US08269346B2
公开(公告)日：2012-09-18
申请号：US13047057
申请日：2011-03-14
申请人： Shoji Seta , Hideaki Ikuma , Yukihito Oowaki
发明人： Shoji Seta , Hideaki Ikuma , Yukihito Oowaki
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L23/3114 , H01L23/525 , H01L24/13 , H01L2224/02375 , H01L2224/02381 , H01L2224/0401 , H01L2224/05548 , H01L2224/05553 , H01L2224/05572 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01077 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A semiconductor device has an LSI chip including a semiconductor substrate, an LSI core section provided at a center portion of the semiconductor substrate and serving as a multilayered wiring layer of the semiconductor substrate, a first rewiring layer provided adjacent to an outer periphery of the LSI core section on the semiconductor substrate and including a plurality of wiring layers, a first pad electrode disposed at an outer periphery of the first rewiring layer, and an insulation layer covering the first pad electrode. The semiconductor device includes a second rewiring layer provided on the LSI chip and including a rewiring connected to the first pad electrode. The semiconductor device includes a plurality of ball electrodes provided on the second rewiring layer. The first rewiring layer is electrically connected to the LSI core section and the first pad electrode.
摘要翻译：半导体器件具有包括半导体衬底的LSI芯片，设置在半导体衬底的中心部分并用作半导体衬底的多层布线层的LSI芯部，与LSI的外周相邻设置的第一重新布线层芯部，并且包括多个布线层，设置在第一重新布线层的外周的第一焊盘电极和覆盖第一焊盘电极的绝缘层。半导体器件包括设置在LSI芯片上并包括连接到第一焊盘电极的重新布线的第二重新布线层。半导体器件包括设置在第二重新布线层上的多个球电极。第一再布线层与LSI芯部和第一焊盘电极电连接。

2. 发明申请

US20080142987A1 COMPUTER AUTOMATED DESIGN SYSTEM, A COMPUTER AUTOMATED DESIGN METHOD, AND A SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：计算机自动设计系统，计算机自动设计方法和半导体集成电路
公开(公告)号：US20080142987A1
公开(公告)日：2008-06-19
申请号：US12036708
申请日：2008-02-25
申请人： Shoji SETA
发明人： Shoji SETA
IPC分类号： H01L23/52
CPC分类号： G06F17/5077 , H01L23/5222 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A computer automated design system includes a subject routing module configured to set a first grid area and a first diagonal grid area and route a first wire in the first grid area and a first diagonal wire extending diagonally to a longitudinal direction of the first wire and a next routing module configured to set a second grid area and a second diagonal grid area and route a second wire in the second grid area and a second diagonal wire extending diagonally to a longitudinal direction of the second wire.
摘要翻译：计算机自动化设计系统包括被配置为设置第一网格区域和第一对角网格区域并且将第一网格布置在第一网格区域中的对象路线模块以及沿第一线材的纵向方向对角延伸的第一对角线材，以及下一路由模块，被配置为设置第二网格区域和第二对角线网格区域，并且将所述第二网格区域中的第二线路布置，并且沿着所述第二线材的纵向方向对角地延伸的第二对角线。

3. 发明授权

US08653629B2 Semiconductor device and wafer 失效
标题翻译：半导体器件和晶圆
公开(公告)号：US08653629B2
公开(公告)日：2014-02-18
申请号：US13236353
申请日：2011-09-19
申请人： Shoji Seta , Yojiro Hamasaki
发明人： Shoji Seta , Yojiro Hamasaki
IPC分类号： H01L23/544
CPC分类号： H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate. The semiconductor device has a plurality of LSI regions that are formed on the semiconductor substrate and are provided with a first power supply wiring layer including a first power supply wire. The semiconductor device has a first power supply terminal formed on the semiconductor substrate. The semiconductor device has a second power supply wiring layer including a second power supply wire that electrically connects the first power supply wire and the first power supply terminal, the second power supply wiring layer is formed in a dicing region between the LSI regions along a dicing line that separates the LSI regions and the dicing line region. A first barrier metal film is formed at least in the LSI regions at a boundary between the first power supply wire and the second power supply wire.
摘要翻译：半导体器件具有半导体衬底。半导体器件具有形成在半导体衬底上的多个LSI区域，并且设置有包括第一电源线的第一电源布线层。半导体器件具有形成在半导体衬底上的第一电源端子。半导体器件具有包括电连接第一电源线和第一电源端子的第二电源线的第二电源布线层，第二电源布线层沿着切割形成在LSI区域之间的切割区域中该线分离LSI区域和切割线区域。至少在LSI区域中在第一电源线和第二电源线之间的边界处形成第一阻挡金属膜。

4. 发明申请

US20110205257A1 SEMICONDUCTOR DEVICE AND DISPLAY DEVICE 审中-公开
标题翻译：半导体器件和显示器件
公开(公告)号：US20110205257A1
公开(公告)日：2011-08-25
申请号：US13102194
申请日：2011-05-06
申请人： Shoji Seta
发明人： Shoji Seta
IPC分类号： G09G5/10 , G09G5/00
CPC分类号： G09G3/3611 , G09G2310/08 , G09G2370/08
摘要： A semiconductor device includes: an LCD controller configured to output a plurality of image signals in parallel; a plurality of signal lines respectively corresponding to the plurality of image signals to be outputted in parallel; a plurality of terminal portions respectively connected to the plurality of signal lines; and delay circuits configured to delay a plurality of image signals, which are divided into a plurality of groups to the extent that the sum of each value of a current flowing through each signal line does not exceed a predetermined current value and outputted from a plurality of terminal portions, by a predetermined delay time from each other among the plurality of groups.
摘要翻译：半导体器件包括：LCD控制器，被配置为并行地输出多个图像信号; 分别对应于要平行输出的多个图像信号的多个信号线; 分别连接到所述多条信号线的多个端子部分; 以及延迟电路，被配置为延迟被分成多个组的多个图像信号，使得流过每个信号线的电流的每个值的和不超过预定电流值，并从多个终端部分在多个组中彼此预定的延迟时间。

5. 发明授权

US07652920B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07652920B2
公开(公告)日：2010-01-26
申请号：US11444537
申请日：2006-06-01
申请人： Shoji Seta , Takeshi Yoshimoto
发明人： Shoji Seta , Takeshi Yoshimoto
IPC分类号： G11C16/06
CPC分类号： H03K19/1776 , H03K19/17764
摘要： A programmable logic device unit, a non-volatile memory unit which stores data for programming the programmable logic device unit in a part of data storage area thereof and a control circuit which controls the non-volatile memory unit to allow the data stored in a part of the data storage area to be read at power-on time and supplied to the programmable logic device unit are integrally provided on a semiconductor chip. Based on the program data, the programmable logic device unit forms an interface for allowing the non-volatile memory unit to operate as at least one of a register, a flash memory, a random access memory, and a read-only memory.
摘要翻译：一种可编程逻辑器件单元，一种非易失性存储器单元，其存储用于将可编程逻辑器件单元编程在其数据存储区域的一部分中的数据;以及控制电路，其控制非易失性存储器单元以允许存储在部件中的数据在电源接通时被读取并提供给可编程逻辑器件单元的数据存储区域被一体地设置在半导体芯片上。基于程序数据，可编程逻辑器件单元形成用于允许非易失性存储器单元作为寄存器，闪速存储器，随机存取存储器和只读存储器中的至少一个来操作的接口。

6. 发明授权

US07370307B2 Computer automated design system, a computer automated design method, and a semiconductor integrated circuit 有权
标题翻译：计算机自动化设计系统，计算机自动化设计方法和半导体集成电路
公开(公告)号：US07370307B2
公开(公告)日：2008-05-06
申请号：US11249388
申请日：2005-10-14
申请人： Shoji Seta
发明人： Shoji Seta
IPC分类号： G06F17/50 , H01L29/40
CPC分类号： G06F17/5077 , H01L23/5222 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A computer automated design system includes a subject routing module configured to set a first grid area and a first diagonal grid area and route a first wire in the first grid area and a first diagonal wire extending diagonally to a longitudinal direction of the first wire and a next routing module configured to set a second grid area and a second diagonal grid area and route a second wire in the second grid area and a second diagonal wire extending diagonally to a longitudinal direction of the second wire.
摘要翻译：计算机自动化设计系统包括被配置为设置第一网格区域和第一对角网格区域并且将第一网格布置在第一网格区域中的对象路线模块以及沿第一线材的纵向方向对角延伸的第一对角线材，以及下一路由模块，被配置为设置第二网格区域和第二对角线网格区域，并且将所述第二网格区域中的第二线路布置，并且沿着所述第二线材的纵向方向对角地延伸的第二对角线材。

7. 发明授权

US07169697B2 Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07169697B2
公开(公告)日：2007-01-30
申请号：US10983746
申请日：2004-11-09
申请人： Shoji Seta , Makoto Sekine , Naofumi Nakamura
发明人： Shoji Seta , Makoto Sekine , Naofumi Nakamura
IPC分类号： H01L21/4763
CPC分类号： H01L21/31116 , H01L21/76802 , H01L21/76808 , H01L21/7681 , H01L21/76811 , H01L21/7682 , H01L21/76825 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/76835 , H01L21/76838 , H01L21/76897 , H01L2221/1031 , H01L2924/30107
摘要： Disclosed is a semiconductor device, comprising a first wiring structure formed on a semiconductor substrate and including a first plug and a first wiring formed on the first plug, and a second wiring structure formed on the semiconductor substrate belonging to the wiring layer equal to the first wiring structure and including a second plug and a second wiring formed on the second plug, wherein the upper surface of the first wiring is positioned higher than the upper surface of the second wiring, and the lower surface of the first wiring is positioned flush with or lower than the upper surface of the second wiring. The present invention also provides a method of manufacturing the particular semiconductor device.
摘要翻译：公开了一种半导体器件，包括形成在半导体衬底上的第一布线结构，包括形成在第一插头上的第一插头和第一布线，以及形成在属于布线层的半导体衬底上的第二布线结构，布线结构，并且包括形成在第二插头上的第二插头和第二布线，其中第一布线的上表面定位成高于第二布线的上表面，并且第一布线的下表面与低于第二布线的上表面。本发明还提供了制造特定半导体器件的方法。

8. 发明授权

US06846750B1 High precision pattern forming method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的高精度图案形成方法
公开(公告)号：US06846750B1
公开(公告)日：2005-01-25
申请号：US09604724
申请日：2000-06-28
申请人： Tokuhisa Ohiwa , Shoji Seta , Nobuo Hayasaka , Katsuya Okumura , Akihiro Kojima , Junko Ohuchi , Tsukasa Azuma , Hideo Ichinose , Ichiro Mizushima
发明人： Tokuhisa Ohiwa , Shoji Seta , Nobuo Hayasaka , Katsuya Okumura , Akihiro Kojima , Junko Ohuchi , Tsukasa Azuma , Hideo Ichinose , Ichiro Mizushima
IPC分类号： H01L21/302 , H01L21/033 , H01L21/30 , H01L21/306 , H01L21/3065 , H01L21/311 , H01L21/316 , H01L21/768 , H01L21/461
CPC分类号： H01L21/76802 , H01L21/0331 , H01L21/31111 , H01L21/31116 , H01L21/31604 , H01L21/31616 , H01L21/76816 , H01L21/7682
摘要： According to the present invention, there is provided a method of manufacturing a semiconductor device, where a soluble thin film which is soluble in a dissolving liquid is used. According to the method of the present invention, when a soluble thin film is formed between a film to be processed which should be patterned and a mask pattern, it becomes possible to remove the mask pattern by lifting-off. On the other hand, when the thin film is used for a dummy layer for forming an air wiring structure, the dummy layer can be removed without performing ashing using oxygen plasma.
摘要翻译：根据本发明，提供一种制造半导体器件的方法，其中使用可溶于溶解液的可溶性薄膜。根据本发明的方法，当在要被图案化的被处理膜和掩模图案之间形成可溶性薄膜时，可以通过剥离来去除掩模图案。另一方面，当薄膜用于形成空气布线结构的虚拟层时，可以去除虚拟层而不用氧等离子体进行灰化。

9. 发明授权

US06607986B2 Dry etching method and semiconductor device manufacturing method 有权
标题翻译：干蚀刻法和半导体器件制造方法
公开(公告)号：US06607986B2
公开(公告)日：2003-08-19
申请号：US09739905
申请日：2000-12-20
申请人： Shoji Seta , Hideo Ichinose
发明人： Shoji Seta , Hideo Ichinose
IPC分类号： H01L21302
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/31138 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： In a method for dry-etching a coating by use of reactive gas which is activated, a second insulating layer containing carbon atoms which is formed on a first insulating layer containing carbon atoms is ashed by use of a gas containing carbon atoms and at least one of oxygen atoms, nitrogen atoms and hydrogen atoms. By using the above gas, the second insulating layer containing carbon atoms which is formed on the first insulating layer which is an underlying layer can be efficiently ashed and removed without removing carbon atoms in the side surface of the grooves formed in the first insulating layer and etching the side surface thereof. Thus, the side surface of the groove formed in the first insulating layer will not be modified or deformed.
摘要翻译：在通过使用被活化的反应性气体干蚀刻涂层的方法中，通过使用含有碳原子的气体和至少一个含有碳原子的气体将形成在含有碳原子的第一绝缘层上的含有碳原子的第二绝缘层灰化的氧原子，氮原子和氢原子。通过使用上述气体，能够有效地除去形成在作为下层的第一绝缘层上的含有碳原子的第二绝缘层，而不除去在第一绝缘层中形成的槽的侧面中的碳原子，蚀刻其侧表面。因此，形成在第一绝缘层中的槽的侧表面将不会改变或变形。

10. 发明授权

US06605542B2 Manufacturing method of semiconductor devices by using dry etching technology 失效
公开(公告)号：US06605542B2
公开(公告)日：2003-08-12
申请号：US09995839
申请日：2001-11-29
申请人： Shoji Seta , Makoto Sekine , Naofumi Nakamura
发明人： Shoji Seta , Makoto Sekine , Naofumi Nakamura
IPC分类号： H01L21391
CPC分类号： H01L21/76829 , H01L21/31116 , H01L21/76808 , H01L21/7681 , H01L21/76811 , H01L21/76826 , H01L21/76835 , H01L21/76838 , H01L21/76897 , H01L2221/1031 , H01L2924/30107
摘要： There is provided a method of forming an interlayer insulating film having a dual-damascene structure, a contact hole and a deep trench mask using an organic silicon film. The shape of polysilane or the like is processed so that polysilane is used as an interlayer insulating film having a dual-damascene structure to control the shape and depth and prevent borderless etching which must be solved when a trench is formed. Polysilane and an insulating film are formed into a laminated structure so as to be integrated with each other after a dry etching step has been completed to easily form a contact hole having a high aspect ratio. The surface of polysilane is selectively formed into an insulating film so as to be used as a mask for use in a dry etching step. Polysilane for use as an anti-reflective film or an etching mask is changed to an oxide film or a nitride film so that films are easily removed. Hence it follows that a device region and a device isolation region of a densely integrated circuit can be smoothed, a self-aligned contact hole and metallization trench can be formed with a satisfactory manufacturing yield and the pattern of a gate electrode can be formed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式