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1. 发明申请

US20130049074A1 METHODS FOR FORMING CONNECTIONS TO A MEMORY ARRAY AND PERIPHERY 审中-公开
标题翻译：用于形成与存储器阵列和外围设备的连接的方法
公开(公告)号：US20130049074A1
公开(公告)日：2013-02-28
申请号：US13216164
申请日：2011-08-23
申请人： Shyam Surthi , Hung-Ming Tsai
发明人： Shyam Surthi , Hung-Ming Tsai
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L27/1052 , H01L27/10826 , H01L27/10879 , H01L27/10894
摘要： Methods are disclosed for forming connections to a memory array and a periphery of the array. The methods include forming stacks of conductive materials on the array and the periphery and forming a step between the periphery stack and the array stack. The step is removed during subsequent processing, and connections are formed from the conductive materials remaining on the array and the periphery. In some embodiments, the step is removed before any photolithographic processes.
摘要翻译：公开了用于形成到阵列的存储器阵列和外围的连接的方法。所述方法包括在阵列和周边上形成导电材料的叠层并在外围堆叠和阵列堆叠之间形成一个台阶。在随后的处理期间移除该步骤，并且由保留在阵列和周边上的导电材料形成连接。在一些实施例中，在任何光刻工艺之前去除该步骤。

2. 发明申请

US20100112191A1 SYSTEMS AND ASSOCIATED METHODS FOR DEPOSITING MATERIALS 审中-公开
标题翻译：用于沉积材料的系统和相关方法
公开(公告)号：US20100112191A1
公开(公告)日：2010-05-06
申请号：US12262036
申请日：2008-10-30
申请人： Zhe Song , Jeffery B. Hull , Shyam Surthi
发明人： Zhe Song , Jeffery B. Hull , Shyam Surthi
IPC分类号： B05D5/12 , C23C16/54
CPC分类号： C23C16/45534 , C23C16/401 , C23C16/4412 , C23C16/45544 , H01L21/67005
摘要： Several embodiments of systems for depositing materials and associated methods of operation are disclosed herein. In one embodiment, the system includes a reaction chamber having an inlet and an outlet, a gas source coupled to the inlet of the reaction chamber, and a neutralizer source coupled to the outlet of the reaction chamber. The gas source contains a first precursor gas, a second precursor gas, and a purge gas. The neutralizer source contains a neutralizing agent configured to reduce a rate of reaction between the first precursor gas and the second precursor gas.
摘要翻译：本文公开了用于沉积材料和相关操作方法的系统的几个实施例。在一个实施例中，系统包括具有入口和出口的反应室，耦合到反应室的入口的气体源和耦合到反应室的出口的中和剂源。气源包含第一前体气体，第二前体气体和净化气体。中和剂源含有中和剂，其被配置为降低第一前体气体和第二前体气体之间的反应速率。

3. 发明授权

US07557013B2 Methods of forming a plurality of capacitors 有权
标题翻译：形成多个电容器的方法
公开(公告)号：US07557013B2
公开(公告)日：2009-07-07
申请号：US11402018
申请日：2006-04-10
申请人： Vishwanath Bhat , Niraj B. Rana , Shyam Surthi
发明人： Vishwanath Bhat , Niraj B. Rana , Shyam Surthi
IPC分类号： H01L21/20 , H01L21/8242 , H01L21/76
CPC分类号： H01L28/91 , H01L27/10852
摘要： A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Conductive material received over the trench sidewall portion is covered with a silicon nitride-comprising layer which less than fills remaining trench volume. The insulative material within the array area and the silicon nitride-comprising layer are etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.
摘要翻译：形成多个电容器的方法包括在电容器阵列区域和电路区域上接收的绝缘材料。阵列区域包括在单独的电容器存储节点位置处接收的绝缘材料内的多个电容器电极开口。中间区域包括沟槽。导电材料形成在开口内并抵靠沟槽的侧壁部分，以小于完全填充沟槽。接收在沟槽侧壁部分上的导电材料覆盖有少于填充剩余沟槽体积的含氮化硅的层。阵列区域内的绝缘材料和含氮化硅的层用液体蚀刻溶液进行蚀刻，该液体蚀刻溶液有效地暴露阵列区域内的导电材料的外侧壁部分，并露出沟槽内的导电材料。阵列区域内的导电材料被并入多个电容器中。

4. 发明申请

US20090042404A1 Semiconductor processing 有权
标题翻译：半导体处理
公开(公告)号：US20090042404A1
公开(公告)日：2009-02-12
申请号：US11891575
申请日：2007-08-10
申请人： Shyam Surthi
发明人： Shyam Surthi
IPC分类号： H01L21/31 , C23C16/00
CPC分类号： C23C16/45546 , C23C16/45578 , C23C16/46 , H01L21/02164 , H01L21/02211 , H01L21/0228 , H01L21/3141 , H01L21/31608
摘要： Embodiments of the present disclosure include semiconductor processing methods and systems. One method includes forming a material layer on a semiconductor substrate by exposing a deposition surface of the substrate to at least a first and a second reactant sequentially introduced into a reaction chamber having an associated process temperature. The method includes removing residual first reactant from the chamber after introduction of the first reactant, removing residual second reactant from the chamber after introduction of the second reactant, and establishing a temperature differential substantially between an edge of the substrate and a center of the substrate via a purge process.
摘要翻译：本公开的实施例包括半导体处理方法和系统。一种方法包括在半导体衬底上形成材料层，方法是将衬底的沉积表面暴露于至少第一和第二反应物，该第一和第二反应物依次导入具有相关工艺温度的反应室中。该方法包括在引入第一反应物之后从室中除去残留的第一反应物，在引入第二反应物之后从室中除去残留的第二反应物，并且基本上在衬底的边缘和衬底的中心之间建立温差清洗过程。

5. 发明申请

US20070238259A1 Methods of forming a plurality of capacitors 有权
标题翻译：形成多个电容器的方法
公开(公告)号：US20070238259A1
公开(公告)日：2007-10-11
申请号：US11402018
申请日：2006-04-10
申请人： Vishwanath Bhat , Niraj Rana , Shyam Surthi
发明人： Vishwanath Bhat , Niraj Rana , Shyam Surthi
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/10852
摘要： A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Conductive material received over the trench sidewall portion is covered with a silicon nitride-comprising layer which less than fills remaining trench volume. The insulative material within the array area and the silicon nitride-comprising layer are etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.
摘要翻译：形成多个电容器的方法包括在电容器阵列区域和电路区域上接收的绝缘材料。阵列区域包括在单独的电容器存储节点位置处接收的绝缘材料内的多个电容器电极开口。中间区域包括沟槽。导电材料形成在开口内并抵靠沟槽的侧壁部分，以小于完全填充沟槽。接收在沟槽侧壁部分上的导电材料覆盖有少于填充剩余沟槽体积的含氮化硅的层。阵列区域内的绝缘材料和含氮化硅的层用液体蚀刻溶液进行蚀刻，该液体蚀刻溶液有效地暴露阵列区域内的导电材料的外侧壁部分，并露出沟槽内的导电材料。阵列区域内的导电材料被并入多个电容器中。

6. 发明授权

US08901631B2 Vertical transistor in semiconductor device and method for fabricating the same 有权
标题翻译：半导体器件中的垂直晶体管及其制造方法
公开(公告)号：US08901631B2
公开(公告)日：2014-12-02
申请号：US13792231
申请日：2013-03-11
申请人： Sheng-Wei Yang , Ying-Cheng Chuang , Shyam Surthi
发明人： Sheng-Wei Yang , Ying-Cheng Chuang , Shyam Surthi
IPC分类号： H01L29/94 , H01L29/06 , H01L21/765
CPC分类号： H01L21/765 , H01L21/265 , H01L21/32055 , H01L21/324 , H01L21/76897 , H01L21/823481 , H01L27/088 , H01L27/1052 , H01L27/10876 , H01L29/0607 , H01L29/407 , H01L29/66666 , H01L29/78 , H01L29/7827
摘要： Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.
摘要翻译：提供一种制造半导体器件的方法，包括以下步骤。提供具有多个支柱的基板，其中围绕每个支柱形成多个沟槽。在衬底中并在每个柱下方形成掺杂区域。去除每个沟槽下方的掺杂区域以形成开口，使得相邻支柱之下的掺杂区域彼此分离。在每个开口中形成屏蔽层。

7. 发明申请

US20140057402A1 Methods of Forming Memory Arrays and Semiconductor Constructions 有权
标题翻译：形成记忆阵列和半导体结构的方法
公开(公告)号：US20140057402A1
公开(公告)日：2014-02-27
申请号：US13591074
申请日：2012-08-21
申请人： Jaydip Guha , Shyam Surthi
发明人： Jaydip Guha , Shyam Surthi
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/10876 , H01L21/02532 , H01L21/0257 , H01L21/02598 , H01L21/26513 , H01L21/324 , H01L21/8222 , H01L21/8229 , H01L21/823487 , H01L27/0814 , H01L27/0823 , H01L27/1021 , H01L27/1022 , H01L27/1052 , H01L27/1085 , H01L27/10894 , H01L27/10897 , H01L29/04 , H01L29/16 , H01L29/6609 , H01L29/66272 , H01L29/66666 , H01L29/732 , H01L29/868
摘要： Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.
摘要翻译：一些实施例包括形成半导体结构的方法。在第一半导体材料内形成重掺杂区，并且在第一半导体材料上外延生长第二半导体材料。将第二半导体材料图案化以形成电路部件，并且对重掺杂区域进行图案化以形成将多个电路部件彼此电耦合的间隔开的掩埋线。至少一些重掺杂区域的图案化与第二半导体材料的至少一些图案化同时发生。

8. 发明授权

US08603891B2 Methods for forming vertical memory devices and apparatuses 有权
标题翻译：用于形成垂直存储器件和装置的方法
公开(公告)号：US08603891B2
公开(公告)日：2013-12-10
申请号：US13354982
申请日：2012-01-20
申请人： Shyam Surthi
发明人： Shyam Surthi
IPC分类号： H01L21/76
CPC分类号： H01L29/7827 , H01L21/76232 , H01L21/764 , H01L27/10876 , H01L27/10891 , H01L29/4236 , H01L29/66666
摘要： Methods of forming vertical memory devices include forming first trenches, at least partially filling the first trenches with a polysilicon material, and forming second trenches generally perpendicular to the first trenches. The second trenches may be formed by removing one of silicon and oxide with a first material removal act and by removing the other of silicon and oxide in a different second material removal act. Methods of forming an apparatus include forming isolation trenches, at least partially filling the isolation trenches with a polysilicon material, and forming word line trenches generally perpendicular to the isolation trenches, the word line trenches having a depth in a word line end region about equal to or greater than a depth thereof in an array region. Word lines may be formed in the word line trenches. Semiconductor devices, vertical memory devices, and apparatuses are formed by such methods.
摘要翻译：形成垂直存储器件的方法包括形成第一沟槽，至少部分地用多晶硅材料填充第一沟槽，以及形成大致垂直于第一沟槽的第二沟槽。可以通过用第一材料去除作用去除硅和氧化物之一并且通过以不同的第二材料去除作用去除另一个硅和氧化物来形成第二沟槽。形成装置的方法包括形成隔离沟槽，至少部分地用多晶硅材料填充隔离沟槽，以及形成大致垂直于隔离沟槽的字线沟槽，字线沟槽在字线端部区域中的深度约等于或大于其在阵列区域中的深度。字线可以形成在字线沟槽中。半导体器件，垂直存储器件和器件通过这种方法形成。

9. 发明授权

US08450175B2 Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith 有权
标题翻译：形成垂直晶体管和至少与其电耦合的导线的方法
公开(公告)号：US08450175B2
公开(公告)日：2013-05-28
申请号：US13031829
申请日：2011-02-22
申请人： Jaydip Guha , Shyam Surthi , Suraj J. Mathew , Kamal M. Karda , Hung-Ming Tsai
发明人： Jaydip Guha , Shyam Surthi , Suraj J. Mathew , Kamal M. Karda , Hung-Ming Tsai
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823487 , H01L27/108 , H01L27/10876 , H01L27/1104 , H01L29/41741 , H01L29/66666 , H01L29/66825 , H01L29/66833
摘要： Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.
摘要翻译：沟槽形成半导体材料。遮蔽材料横向形成在沟槽的至少垂直内侧壁部分上。电导率改性杂质通过沟槽的基底注入到下面的半导体材料中。这种杂质被扩散到横向覆盖在沟槽的顶部内侧壁部分上的掩蔽材料中，并且被扩散到半导体材料中，该半导体材料被容纳在中间通道部分下方的沟槽之间。在中间通道部分下方的半导体材料中形成一个正面内部源极/漏极。内部源极/漏极部分包括在其中具有杂质的沟槽之间的所述半导体材料。导电线横向形成并电耦合到内源/漏的相对侧中的至少一个。栅极形成在导电线的正上方并与导电线隔开并且横向邻近中间通道部分。公开了其他实施例。

10. 发明申请

US20120329274A1 METHOD OF FABRICATING A CELL CONTACT AND A DIGIT LINE FOR A SEMICONDUCTOR DEVICE 有权
标题翻译：细胞接触方法和半导体器件的数字线
公开(公告)号：US20120329274A1
公开(公告)日：2012-12-27
申请号：US13164778
申请日：2011-06-21
申请人： Shyam Surthi , Lars Heineck
发明人： Shyam Surthi , Lars Heineck
IPC分类号： H01L21/28
CPC分类号： H01L27/10855 , H01L27/10885
摘要： The present invention proposes the use of a silicon nitride layer on top of a second conductive layer. After a step of etching a second conductive layer, an oxide spacer is formed to define a gap. Then, another silicon nitride layer fills up the gap. After that, the oxide spacer is removed. Later, a first conductive layer is etched to separate the digit line to cell contact line.
摘要翻译：本发明提出了在第二导电层的顶部上使用氮化硅层。在蚀刻第二导电层的步骤之后，形成氧化物间隔物以限定间隙。然后，另一个氮化硅层填满间隙。之后，除去氧化物间隔物。之后，蚀刻第一导电层以将数字线分隔成细胞接触线。

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