专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20190043969A1 BIDIRECTIONAL BIPOLAR-MODE JFET DRIVER CIRCUITRY 审中-公开
公开(公告)号：US20190043969A1
公开(公告)日：2019-02-07
申请号：US16031752
申请日：2018-07-10
申请人： John WOOD
发明人： John WOOD
IPC分类号： H01L29/732 , H01L29/16 , H01L29/808 , H01L29/10 , H01L29/06 , H03K7/08 , H01L29/08 , H02M3/335 , H01L21/306 , H03K17/60
CPC分类号： H01L29/7322 , H01L21/30604 , H01L27/098 , H01L27/102 , H01L27/1022 , H01L29/0696 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/1058 , H01L29/1095 , H01L29/1608 , H01L29/41708 , H01L29/66901 , H01L29/66916 , H01L29/7395 , H01L29/7802 , H01L29/8083 , H02M1/08 , H02M3/158 , H02M3/1584 , H02M3/33584 , H02M5/297 , H02M7/487 , H02M2001/0006 , H02M2001/0009 , H02M2007/2195 , H02M2007/4815 , H03K7/08 , H03K17/60 , H03K2217/0009
摘要： Double sided versions of several power transistor types are devices that are already known in the literature. Devices built in this configuration are generally required to have a separate driver circuit to control the front and rear control electrodes and provide the gate or base voltage and/or currents for the power switch. This is because there may be of the order of 1000V potential-difference between the frontside and rearside potentials when the transistor is in the off condition—and a single integrated circuit cannot generally sustain this within a single package. The NPN configuration is preferred in this case to benefit from electron conduction for the main power path between the emitters. However, problems arising when using a P-type wafer. The present invention seeks to avoid the use of P-type wafers while still getting the higher conduction performance of NPN operation.

2. 发明申请

US20170236744A1 Array Of Gated Devices And Methods Of Forming An Array Of Gated Devices 审中-公开
公开(公告)号：US20170236744A1
公开(公告)日：2017-08-17
申请号：US15584413
申请日：2017-05-02
申请人： Micron Technology, Inc.
发明人： Marcello D. Mariani , Anna Maria Conti , Sara Vigano
IPC分类号： H01L21/762 , H01L29/423 , H01L27/102 , H01L29/66 , H01L29/78 , H01L27/105 , H01L21/8234 , H01L21/8229
CPC分类号： H01L21/76224 , H01L21/308 , H01L21/8229 , H01L21/823437 , H01L21/823475 , H01L21/823487 , H01L21/8239 , H01L21/8249 , H01L27/1022 , H01L27/1027 , H01L27/1052 , H01L29/4236 , H01L29/42364 , H01L29/66333 , H01L29/66363 , H01L29/66666 , H01L29/744 , H01L29/749 , H01L29/7827
摘要： An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.

3. 发明授权

US09673191B2 Efficient fabrication of BiCMOS devices 有权
公开(公告)号：US09673191B2
公开(公告)日：2017-06-06
申请号：US14659929
申请日：2015-03-17
申请人： Newport Fab, LLC
发明人： Edward Preisler , Todd Thibeault
IPC分类号： H01L27/06 , H01L21/8249 , H01L29/161 , H01L29/417 , H01L27/102 , H01L29/165
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/102 , H01L27/1022 , H01L29/161 , H01L29/165 , H01L29/41708
摘要： A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a PNP bipolar device in a bipolar region, and a spacer clear region defined by an opening in a common spacer layer over the CMOS region and the bipolar region, wherein a sub-collector, a selectively implanted collector, and a base of the PNP bipolar device are formed in the spacer clear region. The PNP bipolar device further includes a collector sinker adjacent to the spacer clear region and electrically connected to the sub-collector of the PNP bipolar device. The BiCMOS device can further include an NPN bipolar device having a sub-collector, a selectively implanted collector and a base in another spacer clear region.

4. 发明授权

US09640528B2 Low-cost complementary BiCMOS integration scheme 有权
公开(公告)号：US09640528B2
公开(公告)日：2017-05-02
申请号：US14659882
申请日：2015-03-17
申请人： Newport Fab, LLC
发明人： Edward Preisler , Todd Thibeault
IPC分类号： H01L27/06 , H01L21/8249 , H01L29/417 , H01L27/102 , H01L29/165
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/102 , H01L27/1022 , H01L29/165 , H01L29/41708
摘要： A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a first CMOS well in the CMOS region, an NPN bipolar device in a bipolar region, a second CMOS well in the bipolar region, the second CMOS well being a collector sinker and being electrically connected to a sub-collector of the NPN bipolar device, where the first CMOS well in the CMOS region and the second CMOS well in the bipolar region form a p-n junction to provide electrical isolation between the CMOS device and the NPN bipolar device. The BiCMOS device further includes a PNP bipolar device having a sub-collector, the sub-collector of the PNP bipolar device being electrically connected to a third CMOS well.

5. 发明申请

US20160049404A1 Array Of Gated Devices And Methods Of Forming An Array Of Gated Devices 有权
标题翻译：门阵列阵列和形成门阵列阵列的方法
公开(公告)号：US20160049404A1
公开(公告)日：2016-02-18
申请号：US14461751
申请日：2014-08-18
申请人： Micron Technology, Inc.
发明人： Marcello Mariani , Anna Maria Conti , Sara Vigano
IPC分类号： H01L27/105 , H01L27/102 , H01L29/78 , H01L21/308 , H01L21/8222 , H01L21/8234 , H01L23/528 , H01L21/768 , H01L27/088 , H01L29/744
CPC分类号： H01L21/76224 , H01L21/308 , H01L21/8229 , H01L21/823437 , H01L21/823475 , H01L21/823487 , H01L21/8239 , H01L21/8249 , H01L27/1022 , H01L27/1027 , H01L27/1052 , H01L29/4236 , H01L29/42364 , H01L29/66333 , H01L29/66363 , H01L29/66666 , H01L29/744 , H01L29/749 , H01L29/7827
摘要： An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.
摘要翻译：门阵列阵列包括排列成行和列的多个选通装置，并且分别包括正面内部区域，内部区域的正上方的中间区域和中部区域的高度外侧区域。多个接入线沿着行的单独侧向靠近中间区域。多条数据/感测线分别在接入线的外侧朝向外侧，并且沿着各列的电极电耦合到外部区域。多个金属线分别在接近线的垂直方向上沿着并且紧邻行的紧邻之间延伸。各个金属线直接抵靠和电耦合到紧邻行中的每一个的内部区域的侧壁。金属线与数据/感测线电隔离。公开了门控器件的其它阵列和形成门控器件阵列的方法。

6. 发明申请

US20130015508A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130015508A1
公开(公告)日：2013-01-17
申请号：US13183442
申请日：2011-07-15
申请人： Wen-Yueh Jang
发明人： Wen-Yueh Jang
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L45/16 , H01L27/1022 , H01L27/1026 , H01L27/226 , H01L27/2436 , H01L27/2463 , H01L29/66272 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/146 , H01L45/147
摘要： A semiconductor device and a method for fabricating the same are described. The semiconductor device includes a well of a first conductive type, first doped regions of a second conductive type, gates of the second conductive type, second doped regions of the first conductive type, and isolation structures. The well is disposed in a substrate. The first doped regions are disposed in the well. The first doped regions are arranged in parallel and extend along a first direction. The gates are disposed on the substrate. The gates are arranged in parallel and extend along a second direction different from the first direction. One of the first doped regions is electrically connected to one of the gates. Each of the second doped regions is disposed in the first doped regions between two adjacent gates. Each of the isolation structures is disposed in the substrate between two adjacent first doped regions.
摘要翻译：对半导体装置及其制造方法进行说明。半导体器件包括第一导电类型的阱，第二导电类型的第一掺杂区域，第二导电类型的栅极，第一导电类型的第二掺杂区域和隔离结构。井设置在基板中。第一掺杂区域设置在阱中。第一掺杂区域平行布置并沿着第一方向延伸。栅极设置在基板上。门平行布置并沿着不同于第一方向的第二方向延伸。第一掺杂区域中的一个电连接到一个栅极。每个第二掺杂区域设置在两个相邻栅极之间的第一掺杂区域中。每个隔离结构设置在两个相邻的第一掺杂区域之间的衬底中。

7. 发明申请

US20120248532A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20120248532A1
公开(公告)日：2012-10-04
申请号：US13515572
申请日：2009-12-18
申请人： Hong-fei Lu
发明人： Hong-fei Lu
IPC分类号： H01L27/088
CPC分类号： H01L27/1022 , H01L29/0696 , H01L29/7395
摘要： Plural island-form emitter cells (22) having a p-base region (23) and an n+ emitter region (24) are provided, distanced from each other, on a main surface of an n− layer (21). A trench (25) deeper than the p-base region (23) is formed on either side of the emitter cell (22). A first gate electrode (26) is embedded in the trench (25) across a first gate insulating film (41). A second gate electrode (27) that electrically connects first gate electrodes (26) is provided, across a second gate insulating film (40), on a surface of a region of the p-base region (23) sandwiched by the n+ emitter region (24). A conductive region (28) that electrically connects second gate electrodes (27) is provided, across a third gate insulating film (42), on a surface of the n− layer (21). A contact region (29) that is isolated from the second gate electrode (27), and that short circuits the n+ emitter region (24) and p-base region (23), is provided.
摘要翻译：在n层（21）的主表面上设置具有p基区域（23）和n +发射极区域（24）的多个岛状发射极单元（22）。在发射电池（22）的两侧形成比p基区域（23）更深的沟槽（25）。第一栅电极（26）跨越第一栅极绝缘膜（41）嵌入沟槽（25）中。在p型基极区域（23）的被n +发射极区域夹着的区域的表面上，在第二栅极绝缘膜（40）之间，设置电连接第一栅电极（26）的第二栅电极（27）（24）。在n层（21）的表面上，跨越第三栅极绝缘膜（42）设置电连接第二栅电极（27）的导电区域（28）。提供了与第二栅电极（27）隔离并且使n +发射极区域（24）和p基极区域（23）短路的接触区域（29）。

8. 发明申请

US20110248382A1 DOUBLE PATTERNING METHOD FOR CREATING A REGULAR ARRAY OF PILLARS WITH DUAL SHALLOW TRENCH ISOLATION 有权
标题翻译：用于创建具有双壁分离分离柱的常规阵列的双重图案方法
公开(公告)号：US20110248382A1
公开(公告)日：2011-10-13
申请号：US13132602
申请日：2008-12-30
申请人： Fabio Pellizzer , Marcello Mariani , Giorgio Servalli
发明人： Fabio Pellizzer , Marcello Mariani , Giorgio Servalli
IPC分类号： H01L27/102 , H01L21/8229
CPC分类号： H01L27/2463 , H01L21/0338 , H01L21/76224 , H01L27/1022 , H01L27/2445 , H01L29/0649 , H01L29/41708 , H01L29/42304 , H01L29/66272 , H01L29/732 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A method is disclosed for forming vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a width below the minimum lithographical resolution F of the lithographic technique employed. In an embodiment, the pillar array features have a dimension of approximately F/2, though this dimension could be reduced down to other values compatible with embodiments of the invention. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars.
摘要翻译：公开了用于形成垂直双极结晶体管的方法，其包括基本接触柱的规则阵列和具有低于所采用的光刻技术的最小光刻分辨率F的宽度的发射极接触柱。在一个实施例中，柱阵列特征具有大约F / 2的尺寸，尽管该尺寸可以减小到与本发明的实施例相容的其它值。诸如相变存储元件的存储元件可以形成在基底接触柱和发射极接触柱的规则阵列上方。

9. 发明授权

US07875513B2 Self-aligned bipolar junction transistors 有权
标题翻译：自对准双极结型晶体管
公开(公告)号：US07875513B2
公开(公告)日：2011-01-25
申请号：US11411311
申请日：2006-04-26
申请人： Fabio Pellizzer , Roberto Bez , Paola Zuliani , Augusto Benvenuti
发明人： Fabio Pellizzer , Roberto Bez , Paola Zuliani , Augusto Benvenuti
IPC分类号： H01L21/82338
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/1022 , H01L27/24 , H01L29/66272
摘要： A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.
摘要翻译：通过形成公共导电区域，在公共导电区域上的自身有效区域中延伸的多个控制区域，多个硅化物保护带和至少一个控制接触区域来形成多个双极晶体管。在第二导电区域和控制接触区域上形成硅化物区域。可以通过在所选择的硅化物保护条的第一侧选择性地注入第一导电类型的掺杂剂区域来形成第二导电区域。通过在所选择的硅化物保护带的第二侧选择性地注入相反的导电型掺杂剂来形成控制接触区域。

10. 发明申请

US20100059829A1 PROCESS FOR MANUFACTURING A MEMORY DEVICE INCLUDING A VERTICAL BIPOLAR JUNCTION TRANSISTOR AND A CMOS TRANSISTOR WITH SPACERS 有权
标题翻译：用于制造包括垂直双极性晶体管的存储器件和具有间隔器的CMOS晶体管的过程
公开(公告)号：US20100059829A1
公开(公告)日：2010-03-11
申请号：US12557396
申请日：2009-09-10
申请人： Fabio Pellizzer , Cristina Casellato , Michele Magistretti , Roberto Colombo , Lucilla Brattico
发明人： Fabio Pellizzer , Cristina Casellato , Michele Magistretti , Roberto Colombo , Lucilla Brattico
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L27/0623 , G11C13/0004 , H01L21/8249 , H01L27/1022 , H01L27/2445 , H01L29/6656 , H01L29/6659 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A bipolar selection transistor and a circuitry MOS transistor for a memory device are formed in a semiconductor body. The bipolar selection transistor is formed by implanting a buried collector, implanting a base region on the buried collector, forming a silicide protection mask on the semiconductor body, and implanting an emitter region and a control contact region. The circuitry MOS transistor is formed by defining a gate on the semiconductor body, forming lateral spacers on the sides of the gate and implanting source and drain regions on the sides of the lateral spacers. Then, a silicide region is formed on the emitter, base contact, source and drain regions and the gate, in a self-aligned way. The lateral spacers are multilayer structures including at least two different layers, one of which is used to form the silicide protection mask on the bipolar selection transistor. Thereby, the dimensions of the lateral spacers are decoupled from the thickness of the silicide protection mask.
摘要翻译：在半导体本体中形成用于存储器件的双极选择晶体管和电路MOS晶体管。双极选择晶体管通过注入掩埋集电器，在掩埋集电极上注入基极区域，在半导体主体上形成硅化物保护掩模，以及注入发射极区域和控制接触区域而形成。电路MOS晶体管通过在半导体主体上限定栅极形成，在栅极的侧面上形成横向间隔物，并在侧面间隔物的侧面上注入源极和漏极区域。然后，以自对准的方式在发射极，基极接触，源极和漏极区域以及栅极上形成硅化物区域。横向间隔物是包括至少两个不同层的多层结构，其中之一用于在双极选择晶体管上形成硅化物保护掩模。因此，横向间隔件的尺寸与硅化物防护罩的厚度分离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式