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1. 发明授权

US08903191B2 Method and apparatus for noise reduction in video 有权
标题翻译：影像降噪方法及装置
公开(公告)号：US08903191B2
公开(公告)日：2014-12-02
申请号：US12317806
申请日：2008-12-30
申请人： Oscar Nestares , Horst W. Haussecker , Scott M. Ettinger , Yoram Gat , Sreenath Kurupati
发明人： Oscar Nestares , Horst W. Haussecker , Scott M. Ettinger , Yoram Gat , Sreenath Kurupati
IPC分类号： G06K9/40 , G06K9/32 , G06K9/36 , H04N5/00 , G06T5/50 , G06T5/00
CPC分类号： G06T5/50 , G06T5/002 , G06T2207/10016 , G06T2207/20028
摘要： In some embodiments, a method of processing a video sequence may include receiving an input video sequence having an input video sequence resolution, aligning images from the input video sequence, reducing noise in the aligned images, and producing an output video sequence from the reduced noise images, wherein the output video sequence has the same resolution as the input video sequence resolution. Other embodiments are disclosed and claimed.
摘要翻译：在一些实施例中，处理视频序列的方法可以包括接收具有输入视频序列分辨率的输入视频序列，对来自输入视频序列的图像，减少对准图像中的噪声，以及从降低的噪声产生输出视频序列图像，其中输出视频序列具有与输入视频序列分辨率相同的分辨率。公开和要求保护其他实施例。

2. 发明授权

US08279240B2 Video scaling techniques 有权
标题翻译：视频缩放技术
公开(公告)号：US08279240B2
公开(公告)日：2012-10-02
申请号：US12286304
申请日：2008-09-29
申请人： Sreenath Kurupati
发明人： Sreenath Kurupati
IPC分类号： G09G5/00 , G06K9/40
CPC分类号： G06T3/4007 , G06T2207/10024 , G06T2207/20012 , H04N1/3935
摘要： A video scaler is disclosed. A polyphase filter can be used to generate interpolated pixels. The values of pixels adjacent an interpolated pixel are examined to determine variation in values among the adjacent pixels to determine minimum and maximum value variations. The value of the interpolated pixel is limited based on the minimum and maximum value variations. Ringing artifacts can be reduced by limiting the color range of an interpolated pixel.
摘要翻译：公开了一种视频缩放器。可以使用多相滤波器来生成内插像素。检查与内插像素相邻的像素的值，以确定相邻像素之间的值的变化，以确定最小值和最大值变化。基于最小值和最大值变化来限制内插像素的值。可以通过限制内插像素的颜色范围来减少振荡伪像。

3. 发明申请

US20100079497A1 Video scaling techniques 有权
标题翻译：视频缩放技术
公开(公告)号：US20100079497A1
公开(公告)日：2010-04-01
申请号：US12286304
申请日：2008-09-29
申请人： Sreenath Kurupati
发明人： Sreenath Kurupati
IPC分类号： G09G5/00
CPC分类号： G06T3/4007 , G06T2207/10024 , G06T2207/20012 , H04N1/3935
摘要： A video scaler is disclosed. A polyphase filter can be used to generate interpolated pixels. The values of pixels adjacent an interpolated pixel are examined to determine variation in values among the adjacent pixels to determine minimum and maximum value variations. The value of the interpolated pixel is limited based on the minimum and maximum value variations. Ringing artifacts can be reduced by limiting the color range of an interpolated pixel.
摘要翻译：公开了一种视频缩放器。可以使用多相滤波器来生成内插像素。检查与内插像素相邻的像素的值，以确定相邻像素之间的值的变化，以确定最小值和最大值变化。基于最小值和最大值变化来限制内插像素的值。可以通过限制内插像素的颜色范围来减少振荡伪像。

4. 发明申请

US20060227152A1 Methods and apparatus for re-scaling image by variable re-scaling factor 失效
公开(公告)号：US20060227152A1
公开(公告)日：2006-10-12
申请号：US11093674
申请日：2005-03-30
申请人： Inaki Berenguer , Raju Hormis , Sreenath Kurupati
发明人： Inaki Berenguer , Raju Hormis , Sreenath Kurupati
IPC分类号： G09G5/00
CPC分类号： G06T3/4084
摘要： A method includes receiving a sequence of samples that represents a row of pixels in an image. The method further includes selecting a re-scaling factor for at least a portion of the row of pixels. The method further includes selecting a filter from a bank of low pass filters based on the selected re-scaling factor, and low-pass filtering the sequence of samples with the selected filter. The method further includes up-sampling the low-pass-filtered sequence of samples by a factor M with a polyphase filter bank having a windowed sinc(t) characteristic to the up-sampled sequence of samples, and down-sampling the polyphase-filtered sequence of samples.

5. 发明申请

US20060020718A1 Resource sharing apparatus, systems, and methods 审中-公开
标题翻译：资源共享设备，系统和方法
公开(公告)号：US20060020718A1
公开(公告)日：2006-01-26
申请号：US10880153
申请日：2004-06-28
申请人： Nicholas Duresky , Sreenath Kurupati
发明人： Nicholas Duresky , Sreenath Kurupati
IPC分类号： G06F3/00
CPC分类号： G06F13/4059
摘要： An apparatus and a system, as well as a method and article, may operate to interchangeably store audio data associated with an audio interface protocol selected from a plurality of audio interface protocols in a polymorphic memory structure capable of being coupled to a common digital input-output interface.
摘要翻译：装置和系统以及方法和文章可以操作以可互换地存储与在多个存储器结构中选择的音频接口协议相关联的音频数据，该多态存储器结构能够耦合到公共数字输入 - 输出接口。

6. 发明授权

US06842791B2 Method and apparatus for memory efficient fast VLAN lookups and inserts in hardware-based packet switches 失效
标题翻译：用于内存高效快速VLAN查找和基于硬件的数据包交换机插入的方法和装置
公开(公告)号：US06842791B2
公开(公告)日：2005-01-11
申请号：US10103470
申请日：2002-03-20
申请人： Muraleedhara H. Navada , Sreenath Kurupati
发明人： Muraleedhara H. Navada , Sreenath Kurupati
IPC分类号： H04L12/46 , G06F13/00
CPC分类号： H04L12/4645 , H04L45/745
摘要： A technique for decreasing VLAN lookup times in hardware-based packet switches by emulating the functionality of a content addressable memory (CAM) with software and random access memories (RAM). The decrease in lookup time is achieved by using content from the data packet to index directly into a table that stores forwarding information. Since the forwarding information is addressed directly by content from the packet, the need to spend time and resources sorting through the table of forwarding information with a key search is eliminated.
摘要翻译：一种通过使用软件和随机存取存储器（RAM）模拟内容可寻址存储器（CAM）的功能来减少基于硬件的分组交换机中的VLAN查找时间的技术。查找时间的减少是通过使用数据包中的内容直接索引到存储转发信息的表中实现的。由于转发信息是通过来自分组的内容直接寻址的，消除了通过密钥搜索通过转发信息表来花费时间和资源排序的需要。

7. 发明授权

US06609234B2 Ordering binary decision diagrams used in the formal equivalence verification of digital designs 有权
标题翻译：订购二进制决策图，用于数字设计的正式等价验证
公开(公告)号：US06609234B2
公开(公告)日：2003-08-19
申请号：US09895919
申请日：2001-06-29
申请人： Sreenath Kurupati
发明人： Sreenath Kurupati
IPC分类号： G06F1750
CPC分类号： G06F17/504
摘要： A method for ordering input variables in binary decision diagrams is described. Once a plurality of disjoint sets of input variables can be found from the sub-equations of a Boolean function, an initial top-level order can be used to form a significantly smaller diagram. The diagram can by reduced further by application of the method recursively on the sub-equations and successive sub-equations until primary inputs are reached.
摘要翻译：描述了用于在二进制决策图中排序输入变量的方法。一旦可以从布尔函数的子方程中找到多个不相交的输入变量集合，则可以使用初始顶级顺序来形成明显更小的图。该图可以通过在子方程和连续子方程上递归地应用该方法，直到达到主要输入。

8. 发明授权

US09773477B2 Reducing the number of scaling engines used in a display controller to display a plurality of images on a screen 有权
公开(公告)号：US09773477B2
公开(公告)日：2017-09-26
申请号：US13997440
申请日：2011-12-29
申请人： Wujian Zhang , Sreenath Kurupati
发明人： Wujian Zhang , Sreenath Kurupati
IPC分类号： G09G5/397 , G09G5/36 , H04N5/46 , H04N21/414 , H04N21/426 , H04N21/431 , H04N21/4402 , G06T3/40
CPC分类号： G09G5/397 , G06T3/40 , G09G5/363 , G09G2340/0407 , G09G2340/10 , G09G2340/12 , G09G2352/00 , G09G2360/06 , G09G2370/20 , H04N5/46 , H04N21/41407 , H04N21/42653 , H04N21/431 , H04N21/440263
摘要： Methods and apparatuses to reduce the number of scaling engines used in a display controller that displays image content associated with a plurality of image sources on a screen are provided. A first multiplexer may receive image content from a plurality of storage devices, and select first image content from one of the plurality of image sources. A first scaling engine may process the selected first image content, wherein a plurality of multiplexers can receives an output of the first scaling engine and the image content from the plurality of storage devices, respectively. Each one of the plurality of multiplexers may output either the image content input to the multiplexer or the output of the first scaling engine depending on which image content was scaled by the first scaling engine. Additionally, a plurality of post-processors may perform additional post-processing on the output of the plurality of multiplexer, respectively.

9. 发明授权

US07542535B2 Method and apparatus for recovering a clock signal 失效
标题翻译：用于恢复时钟信号的方法和装置
公开(公告)号：US07542535B2
公开(公告)日：2009-06-02
申请号：US10880969
申请日：2004-06-30
申请人： Sreenath Kurupati
发明人： Sreenath Kurupati
IPC分类号： H04L7/02
CPC分类号： H03L7/00 , H04L7/033 , H04L7/041 , H04L7/042 , H04L7/10
摘要： A method includes receiving a serial data signal including a preamble and an embedded clock signal having an embedded clock signal frequency, and processing the preamble using logic to determine the embedded clock signal frequency. An apparatus includes a counter unit, a state machine, and a logic unit. The counter unit includes a data port, a clock port and a plurality of counters. In operation, the data port receives a serial data signal and the clock port receives a clock signal having a clock signal frequency. The serial data signal includes a preamble and an embedded clock signal having an embedded clock signal frequency. The state machine identifies at least one of the plurality of counters to count between transitions in the preamble in response to the clock signal. The logic unit is coupled to the plurality of counters and determines the embedded clock signal frequency.
摘要翻译：一种方法包括接收包括具有嵌入式时钟信号频率的前导码和嵌入式时钟信号的串行数据信号，以及使用逻辑处理前导码以确定嵌入式时钟信号频率。一种装置，包括计数器单元，状态机和逻辑单元。计数器单元包括数据端口，时钟端口和多个计数器。在操作中，数据端口接收串行数据信号，时钟端口接收具有时钟信号频率的时钟信号。串行数据信号包括具有嵌入式时钟信号频率的前导码和嵌入式时钟信号。状态机识别多个计数器中的至少一个以响应于时钟信号在前同步码中的转换之间进行计数。逻辑单元耦合到多个计数器并确定嵌入式时钟信号频率。

10. 发明授权

US07467151B2 Method and data structure for a low memory overhead database 有权
标题翻译：低内存开销数据库的方法和数据结构
公开(公告)号：US07467151B2
公开(公告)日：2008-12-16
申请号：US11339247
申请日：2006-01-25
申请人： Sreenath Kurupati , Miguel A. Guerrero
发明人： Sreenath Kurupati , Miguel A. Guerrero
IPC分类号： G06F17/30
CPC分类号： G06F17/30595 , G06F17/30607 , Y10S707/99933 , Y10S707/99934 , Y10S707/99942 , Y10S707/99943 , Y10S707/99944 , Y10S707/99945
摘要： A data structure for use in database applications. The data structure includes a key database that is searchable via an index table.
摘要翻译：用于数据库应用程序的数据结构。数据结构包括可通过索引表搜索的密钥数据库。

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