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1. 发明授权

US07595241B2 Method for fabricating silicon carbide vertical MOSFET devices 有权
标题翻译：制造碳化硅垂直MOSFET器件的方法
公开(公告)号：US07595241B2
公开(公告)日：2009-09-29
申请号：US11466488
申请日：2006-08-23
申请人： Kevin Sean Matocha , Jody Alan Fronheiser , Larry Burton Rowland , Jesse Berkley Tucker , Stephen Daley Arthur , Zachary Matthew Stum
发明人： Kevin Sean Matocha , Jody Alan Fronheiser , Larry Burton Rowland , Jesse Berkley Tucker , Stephen Daley Arthur , Zachary Matthew Stum
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/1608 , H01L29/41766 , H01L29/66068
摘要： A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.
摘要翻译：形成垂直MOSFET器件的方法包括在漂移层衬底内形成沟槽，漂移层包括第一极性类型，沟槽通常限定与第一极性类型相反的第二极性类型的阱区。欧姆接触层形成在沟槽的底表面内，欧姆接触层包括第二极性类型的材料。在漂移层，沟槽的侧壁表面和欧姆接触层上外延生长第二极性类型的层。第一极性类型的层在第二极性类型的外延生长层上外延生长，以便重新填充沟槽，并且将第一和第二极性类型的外延生长层平坦化，以暴露出第二极性类型的上表面漂移层基板。

2. 发明申请

US20080146004A1 SILICON CARBIDE DEVICES AND METHOD OF MAKING 失效
标题翻译：碳化硅器件及其制造方法
公开(公告)号：US20080146004A1
公开(公告)日：2008-06-19
申请号：US11610199
申请日：2006-12-13
申请人： Kevin Sean Matocha , Vinayak Tilak , Stephen Daley Arthur , Zachary Matthew Stum
发明人： Kevin Sean Matocha , Vinayak Tilak , Stephen Daley Arthur , Zachary Matthew Stum
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/0465 , H01L29/66068
摘要： A method for fabricating a SiC MOSFET is disclosed. The method includes growing a SiC epilayer over a substrate, planarizing the SiC epilayer to provide a planarized SiC epilayer, and forming a gate dielectric layer in contact with the planarized epilayer.
摘要翻译：公开了一种制造SiC MOSFET的方法。该方法包括在衬底上生长SiC外延层，平面化SiC外延层以提供平坦化的SiC外延层，以及形成与平坦化的外延层接触的栅极电介质层。

3. 发明授权

US09576868B2 Semiconductor device and method for reduced bias temperature instability (BTI) in silicon carbide devices 有权
标题翻译：用于降低碳化硅器件中偏置温度不稳定性（BTI）的半导体器件和方法
公开(公告)号：US09576868B2
公开(公告)日：2017-02-21
申请号：US13562029
申请日：2012-07-30
申请人： Joseph Darryl Michael , Stephen Daley Arthur
发明人： Joseph Darryl Michael , Stephen Daley Arthur
IPC分类号： H01L21/56 , H01L23/04 , H01L21/50 , H01L29/78 , H01L29/16
CPC分类号： H01L23/04 , H01L21/50 , H01L29/1608 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： A system includes a silicon carbide (SiC) semiconductor device and a hermetically sealed packaging enclosing the SiC semiconductor device. The hermetically sealed packaging is configured to maintain a particular atmosphere near the SiC semiconductor device. Further, the particular atmosphere limits a shift in a threshold voltage of the SiC semiconductor device to less than 1 V during operation.
摘要翻译：一种系统包括碳化硅（SiC）半导体器件和封装SiC半导体器件的密封封装。密封的封装构造成在SiC半导体器件附近保持特定的气氛。此外，特定的气氛限制了在工作期间SiC半导体器件的阈值电压移动到小于1V。

4. 发明申请

US20140027782A1 SEMICONDUCTOR DEVICE AND METHOD FOR REDUCED BIAS TEMPERATURE INSTABILITY (BTI) IN SILICON CARBIDE DEVICES 有权
标题翻译：半导体器件及其在半导体器件中降低偏温不稳定性（BTI）的方法
公开(公告)号：US20140027782A1
公开(公告)日：2014-01-30
申请号：US13562029
申请日：2012-07-30
申请人： Joseph Darryl Michael , Stephen Daley Arthur
发明人： Joseph Darryl Michael , Stephen Daley Arthur
IPC分类号： H01L21/56 , H01L29/78 , H01L29/16
CPC分类号： H01L23/04 , H01L21/50 , H01L29/1608 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： A system includes a silicon carbide (SiC) semiconductor device and a hermetically sealed packaging enclosing the SiC semiconductor device. The hermetically sealed packaging is configured to maintain a particular atmosphere near the SiC semiconductor device. Further, the particular atmosphere limits a shift in a threshold voltage of the SiC semiconductor device to less than 1 V during operation.
摘要翻译：一种系统包括碳化硅（SiC）半导体器件和封装SiC半导体器件的密封封装。密封的封装构造成在SiC半导体器件附近保持特定的气氛。此外，特定的气氛限制了在工作期间SiC半导体器件的阈值电压移动到小于1V。

5. 发明申请

US20130323873A1 OPTICALLY TRIGGERED SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME 有权
标题翻译：光学触发式半导体器件及其制造方法
公开(公告)号：US20130323873A1
公开(公告)日：2013-12-05
申请号：US13960971
申请日：2013-08-07
申请人： AHMED ELASSER , STEPHEN DALEY ARTHUR , ALEXEY VERT , STANISLAV IVANOVICH SOLOVIEV , PETER ALMERN LOSEE
发明人： AHMED ELASSER , STEPHEN DALEY ARTHUR , ALEXEY VERT , STANISLAV IVANOVICH SOLOVIEV , PETER ALMERN LOSEE
IPC分类号： H01L31/111
CPC分类号： H01L31/1113 , H01L27/0817 , H01L29/74
摘要： A thyristor device includes a semiconductor body and a conductive anode. The semiconductor body has a plurality of doped layers forming a plurality of dopant junctions and includes an optical thyristor, a first amplifying thyristor, and a switching thyristor. The conductive anode is disposed on a first side of the semiconductor body. The optical thyristor is configured to receive incident radiation to generate a first electric current, and the first amplifying thyristor is configured to increase the first electric current from the optical thyristor to at least a threshold current. The switching thyristor switches to the conducting state in order to conduct a second electric current from the anode and through the semiconductor body.
摘要翻译：晶闸管器件包括半导体本体和导电阳极。半导体本体具有形成多个掺杂剂结的多个掺杂层，并且包括光学晶闸管，第一放大晶闸管和开关晶闸管。导电阳极设置在半导体本体的第一侧上。光晶闸管被配置为接收入射辐射以产生第一电流，并且第一放大晶闸管被配置为将来自光晶闸管的第一电流增加到至少阈值电流。开关晶闸管切换到导通状态，以便从阳极和半导体本体传导第二电流。

6. 发明申请

US20130221374A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130221374A1
公开(公告)日：2013-08-29
申请号：US13597299
申请日：2012-08-29
申请人： Ramakrishna Rao , Stephen Daley Arthur , Peter Almern Losee , Kevin Sean Matocha
发明人： Ramakrishna Rao , Stephen Daley Arthur , Peter Almern Losee , Kevin Sean Matocha
IPC分类号： H01L29/16
CPC分类号： H01L29/1608 , H01L29/0615 , H01L29/1095 , H01L29/66068 , H01L29/66712 , H01L29/7802 , H01L29/7811
摘要： A semiconductor device includes a substrate comprising a semiconductor material. The substrate has a surface that defines a surface normal direction and includes a P-N junction comprising an interface between a first region and a second region, where the first (second) region includes a first (second) dopant type, so as to have a first (second) conductivity type. The substrate includes a termination extension region disposed adjacent to the P-N junction and having an effective concentration of the second dopant type that is generally the effective concentration of the second dopant type in the second doped region. The substrate includes an adjust region disposed adjacent to the surface and between the surface and at least part of the termination extension region, where the effective concentration of the second dopant type generally decreases when moving from the termination extension region into the adjust region along the surface normal direction.
摘要翻译：半导体器件包括包含半导体材料的衬底。衬底具有限定表面法线方向的表面，并且包括PN结，其包括在第一区域和第二区域之间的界面，其中第一（第二）区域包括第一（第二）掺杂剂类型，以便具有第一（第二）导电类型。衬底包括邻近P-N结设置并且具有通常为第二掺杂区域中的第二掺杂剂类型的有效浓度的第二掺杂剂类型的有效浓度的终止延伸区域。衬底包括与表面相邻并且在表面与终止延伸区域的至少一部分之间布置的调节区域，其中当从端接延伸区域沿着表面移动到调节区域中时，第二掺杂剂类型的有效浓度通常降低正常方向

7. 发明授权

US08377756B1 Silicon-carbide MOSFET cell structure and method for forming same 有权
标题翻译：碳化硅MOSFET单元结构及其形成方法
公开(公告)号：US08377756B1
公开(公告)日：2013-02-19
申请号：US13190723
申请日：2011-07-26
申请人： Stephen Daley Arthur , Kevin Matocha , Peter Sandvik , Zachary Stum , Peter Losee , James McMahon
发明人： Stephen Daley Arthur , Kevin Matocha , Peter Sandvik , Zachary Stum , Peter Losee , James McMahon
IPC分类号： H01L29/10 , H01L29/76
CPC分类号： H01L27/088 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7802
摘要： In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (228) (P type) and two parallel sources (260) (N type) formed within the well. A plurality of source rungs (262) (doped N) connect sources (260) at multiple locations. Regions between two rungs (262) comprise a body (252) (P type). These features are formed on an N-type epitaxial layer (220), which is formed on an N-type substrate (216). A contact (290) extends across and contacts a plurality of source rungs (262) and bodies (252). Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.
摘要翻译：在一个实施例中，本发明包括一个包含单个MOSFET单元的MOSFET。每个单元包括形成在孔内的U形孔（228）（P型）和两个平行源（260）（N型）。多个源极（262）（掺杂N）在多个位置连接源极（260）。两个梯级（262）之间的区域包括主体（252）（P型）。这些特征形成在形成在N型衬底（216）上的N型外延层（220）上。接触件（290）跨越并接触多个源极（262）和主体（252）。栅极氧化物和栅极接触覆盖第一阱的支腿和第二相邻阱的支路，响应于栅极电压而反转导电性。 MOSFET包括多个这些单元以获得期望的低通道电阻。在制造过程的几个状态下使用自对准技术形成单元区域。

8. 发明申请

US20120153362A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120153362A1
公开(公告)日：2012-06-21
申请号：US12971188
申请日：2010-12-17
申请人： Zachary Matthew Stum , Stephen Daley Arthur , Kevin Sean Matocha , Peter Almern Losee
发明人： Zachary Matthew Stum , Stephen Daley Arthur , Kevin Sean Matocha , Peter Almern Losee
IPC分类号： H01L29/772 , H01L21/265
CPC分类号： H01L29/36 , H01L21/046 , H01L29/1608 , H01L29/66068 , H01L29/7816 , H01L29/7827
摘要： A method comprising, introducing a dopant type into a semiconductor layer to define a well region of the semiconductor layer, the well region comprising a channel region, and introducing a dopant type into the well region to define a multiple implant region substantially coinciding with the well region but excluding the channel region.
摘要翻译：一种方法，包括：将掺杂剂类型引入到半导体层中以限定所述半导体层的阱区，所述阱区包括沟道区，并且将掺杂剂类型引入所述阱区以限定与所述阱大致重合的多个注入区但不包括渠道区域。

9. 发明授权

US08049338B2 Power semiconductor module and fabrication method 有权
标题翻译：功率半导体模块及其制造方法
公开(公告)号：US08049338B2
公开(公告)日：2011-11-01
申请号：US11279011
申请日：2006-04-07
申请人： Eladio Clemente Delgado , Richard Alfred Beaupre , Stephen Daley Arthur , Ernest Wayne Balch , Kevin Matthew Durocher , Paul Alan McConnelee , Raymond Albert Fillion
发明人： Eladio Clemente Delgado , Richard Alfred Beaupre , Stephen Daley Arthur , Ernest Wayne Balch , Kevin Matthew Durocher , Paul Alan McConnelee , Raymond Albert Fillion
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L25/50 , H01L23/5389 , H01L24/24 , H01L24/29 , H01L24/82 , H01L24/83 , H01L25/072 , H01L25/16 , H01L2224/04105 , H01L2224/2413 , H01L2224/24137 , H01L2224/2518 , H01L2224/2919 , H01L2224/73267 , H01L2224/82039 , H01L2224/82047 , H01L2224/83192 , H01L2224/83801 , H01L2224/8385 , H01L2224/92144 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/12044 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15153 , H01L2924/1517 , H01L2924/15192 , H01L2924/1532 , H01L2924/18162 , H01L2924/00 , H01L2924/01014
摘要： A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.
摘要翻译：功率半导体模块包括：互连层，其包括在电介质层上图案化的电导体，所述电导体包括具有足以承载电力电流的厚度的功率耦合部分和具有比功率耦合的厚度更薄的厚度的控制耦合部分一部分; 以及物理耦合到所述互连层并且电耦合到所述电导体的功率耦合部分的半导体功率器件。

10. 发明授权

US07829402B2 MOSFET devices and methods of making 有权
标题翻译： MOSFET器件及其制造方法
公开(公告)号：US07829402B2
公开(公告)日：2010-11-09
申请号：US12368498
申请日：2009-02-10
申请人： Kevin Sean Matocha , Stephen Daley Arthur , Ramakrishna Rao , Peter Almern Losee , Zachary Matthew Stum
发明人： Kevin Sean Matocha , Stephen Daley Arthur , Ramakrishna Rao , Peter Almern Losee , Zachary Matthew Stum
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7802 , H01L21/0465 , H01L29/0615 , H01L29/1095 , H01L29/1608 , H01L29/2003 , H01L29/41766 , H01L29/66068 , H01L29/66727
摘要： A MOSFET device and a method for fabricating MOSFET devices are disclosed. The method includes providing a semiconductor device structure including a semiconductor device layer of a first conductivity type, and ion implanting a well structure of a second conductivity type in the semiconductor device layer, where the ion implanting includes providing a dopant concentration profile in a single mask implant sequence.
摘要翻译：公开了MOSFET器件和用于制造MOSFET器件的方法。该方法包括提供包括第一导电类型的半导体器件层和在半导体器件层中离子注入第二导电类型的阱结构的半导体器件结构，其中离子注入包括在单个掩模中提供掺杂剂浓度分布植入序列。

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