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1. 发明授权

US08438521B1 Methods and apparatus for implementing application specific processors 有权
标题翻译：用于实现应用程序特定处理器的方法和装置
公开(公告)号：US08438521B1
公开(公告)日：2013-05-07
申请号：US12130679
申请日：2008-05-30
申请人： Robert Jackson , Steven Perry
发明人： Robert Jackson , Steven Perry
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Methods and apparatus are provided for efficiently implementing an application specific processor. An application specific processor includes a data path and a control path. A control path is implemented using processor components to increase resource efficiency. Both the data path and the control path can be implemented using function units that are selected, parameterized, and interconnected. A tool uses the selected function units and interconnection information to provide data for implementing the application specific processor. Missing function units or interconnections can be identified and corrected.
摘要翻译：提供了用于有效实施专用处理器的方法和装置。专用处理器包括数据路径和控制路径。使用处理器组件实现控制路径以提高资源效率。可以使用被选择，参数化和互连的功能单元来实现数据路径和控制路径。工具使用所选择的功能单元和互连信息来提供用于实现专用处理器的数据。可以识别和纠正缺少的功能单元或互连。

2. 发明授权

US08397185B1 Graphical user aid for technology migration and associated methods 有权
标题翻译：用于技术迁移和相关方法的图形用户帮助
公开(公告)号：US08397185B1
公开(公告)日：2013-03-12
申请号：US13461040
申请日：2012-05-01
申请人： Steven Perry , Jinyong Yuan , Shih-Yueh Lin , John R. Chase
发明人： Steven Perry , Jinyong Yuan , Shih-Yueh Lin , John R. Chase
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.
摘要翻译：提供了可用于将源设备（例如可编程逻辑设计（PLD或FPGA））迁移到目标设备（诸如等效或替代专用集成电路（ASIC））中的图形用户辅助。提供了一种设备选择器指南，用于在完成迁移之前评估从源设备到目标设备的迁移前景。

3. 发明申请

US20130061247A1 PROCESSOR TO MESSAGE-BASED NETWORK INTERFACE USING SPECULATIVE TECHNIQUES 有权
标题翻译：基于信息的网络接口处理器采用分析技术
公开(公告)号：US20130061247A1
公开(公告)日：2013-03-07
申请号：US13369727
申请日：2012-02-09
申请人： Steven Perry , Gareth Duncan
发明人： Steven Perry , Gareth Duncan
IPC分类号： G06F3/00
CPC分类号： G06F13/385 , G06F2213/3808 , H04L49/90
摘要： Methods and systems are provided for a message network interface unit (a message interface unit), coupled to a processor, that is used for allowing the processor to send messages to a hardware unit. Methods and systems are also provided for a message interface unit, coupled to a processor, that is used for allowing a processor to receive messages from a hardware unit. The message network interface unit described herein may allow for the implementation data-intensive, real time applications, which require a substantially low message response latency and a substantially high message throughput.
摘要翻译：提供了一种方法和系统，用于耦合到处理器的消息网络接口单元（消息接口单元），其用于允许处理器向硬件单元发送消息。还提供了一种方法和系统，用于耦合到处理器的消息接口单元，其用于允许处理器从硬件单元接收消息。本文描述的消息网络接口单元可以允许执行数据密集型实时应用，其需要基本上低的消息响应延迟和基本上高的消息吞吐量。

4. 发明申请

US20130049951A1 FIRE ALARM POWER LINE CARRIER COM-SYSTEM 失效
标题翻译：火警报警电源线载波系统
公开(公告)号：US20130049951A1
公开(公告)日：2013-02-28
申请号：US13320497
申请日：2011-05-12
申请人： Christopher George Kalivas , Steven Perry Apelman
发明人： Christopher George Kalivas , Steven Perry Apelman
IPC分类号： G08B1/08
CPC分类号： G08B25/06 , G08B17/00 , G08B17/06 , G08B17/10 , G08B17/113
摘要： A fire alarm system 4 for a structure, has a two-wire interconnected transceiver 4J that uses power line carrier technology to inject a radio signal onto two power conductors, 6B & 6W. The transceiver 4J includes a transmitter circuit 7 and a receiver circuit 9. The transmitter circuit 7 includes a trigger circuit 10, attachable to an output line of a local fire alarm 5. The trigger circuit 10, can monitor the output line (6 Yellow) for an alarm condition output signal, for the purpose of sensing an alarm condition. The transmitter circuit 7 responds to the alarm condition output signal by injecting the radio signal onto the two power conductors. The radio signal would activate a second fire alarm system 4B attached to power lines in the structure.
摘要翻译：用于结构的火灾报警系统4具有使用电力线载波技术将无线电信号注入到两个电力导体6B和6W上的两线互连收发器4J。收发机4J包括发射机电路7和接收机电路9.发射机电路7包括可附接到本地火警5的输出线的触发电路10.触发电路10可以监视输出线（6黄色）用于报警条件输出信号，用于感测报警条件。发射机电路7通过将无线电信号注射到两个电力导体上来响应报警条件输出信号。无线电信号将激活附接到结构中的电力线的第二火灾报警系统4B。

5. 发明授权

US08191020B1 Graphical user aid for technology migration and associated methods 有权
标题翻译：用于技术迁移和相关方法的图形用户帮助
公开(公告)号：US08191020B1
公开(公告)日：2012-05-29
申请号：US12612479
申请日：2009-11-04
申请人： Steven Perry , Jinyong Yuan , Shih Yueh Lin , John R. Chase
发明人： Steven Perry , Jinyong Yuan , Shih Yueh Lin , John R. Chase
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.
摘要翻译：提供了可用于将源设备（诸如可编程逻辑设计（PLD或FPGA））迁移到目标设备（诸如等效或代替应用专用集成电路（ASIC））中的图形用户辅助。提供了一种设备选择器指南，用于在完成迁移之前评估从源设备到目标设备的迁移前景。

6. 发明授权

US08060729B1 Software based data flows addressing hardware block based processing requirements 有权
标题翻译：基于软件的数据流解决基于硬件块的处理要求
公开(公告)号：US08060729B1
公开(公告)日：2011-11-15
申请号：US12244904
申请日：2008-10-03
申请人： Steven Perry , Martin Roberts , Kellie Marks
发明人： Steven Perry , Martin Roberts , Kellie Marks
IPC分类号： G06F9/00
CPC分类号： G06F15/7892
摘要： In the provided architecture, one or more multi-threaded processors may be combined with hardware blocks having increased functionality. Each hardware block may be able to transfer a data packet to a particular hardware block based on the packet being processing. One or more hardware block may also be able to divide packets into subpackets for separate processing, and other hardware blocks may be able to rejoin the subpackets. Hardware blocks may also be able to transfer packet information between other hardware blocks during the processing sequence.
摘要翻译：在所提供的架构中，一个或多个多线程处理器可以与具有增加的功能的硬件块组合。每个硬件块可能能够基于正在处理的分组将数据分组传送到特定的硬件块。一个或多个硬件块还可能能够将分组划分为子分组以进行单独处理，并且其他硬件块可能能够重新加入子分组。硬件块也可以在处理序列期间在其它硬件块之间传送分组信息。

7. 发明授权

US08006074B1 Methods and apparatus for executing extended custom instructions 有权
标题翻译：用于执行扩展定制指令的方法和设备
公开(公告)号：US08006074B1
公开(公告)日：2011-08-23
申请号：US10745987
申请日：2003-12-24
申请人： Tracy Miranda , Steven Perry
发明人： Tracy Miranda , Steven Perry
IPC分类号： G06F9/00
CPC分类号： G06F9/30181 , G06F9/3867 , G06F9/3877
摘要： Methods and apparatus are provided for efficiently executing extended custom instructions on a programmable chip. Components of a processor core such as arithmetic logic units, program sequencer units, and address generation units are integrated with customizable logic blocks. Various customizable logic blocks can be invoked in a pipelined manner using an available customized instruction set while allowing a processor to continue simultaneous operation. Program counter snooping is also provided to add custom instruction functionality to a processor with no additional provisions for adding custom instructions.
摘要翻译：提供了用于在可编程芯片上有效执行扩展定制指令的方法和装置。诸如算术逻辑单元，程序定序器单元和地址生成单元的处理器核心的组件与可定制的逻辑块集成。可以使用可用的定制指令集以流水线的方式调用各种可定制的逻辑块，同时允许处理器继续同时操作。还提供了程序计数器窥探功能，可以为处理器添加自定义指令功能，而无需额外增加自定义指令。

8. 发明授权

US08001509B2 Method for programming a mask-programmable logic device and device so programmed 有权
标题翻译：用于编程掩码可编程逻辑器件和如此编程的器件的方法
公开(公告)号：US08001509B2
公开(公告)日：2011-08-16
申请号：US11858060
申请日：2007-09-19
申请人： Steven Perry , Gregor Nixon , Larry Kong , Alasdair Scott , Andrew Hall , Lingli Wang , Chris Dettmar , Jonathan Park , Richard Price
发明人： Steven Perry , Gregor Nixon , Larry Kong , Alasdair Scott , Andrew Hall , Lingli Wang , Chris Dettmar , Jonathan Park , Richard Price
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5054
摘要： A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.
摘要翻译：可以在可比较或兼容的用户可编程逻辑器件（“UPLD”）上设计用于掩模可编程逻辑器件（“MPLD”）的用户逻辑设计并迁移到MPLD，或者可以直接设计在MPLD上。如果设计是在UPLD上设计的，则会考虑目标MPLD的约束，即设备之间的差异，以便迁移将成功。如果设计直接在MPLD上设计，则如果用户指示设计将迁移到UPLD进行测试，则会考虑可比较的兼容UPLD的约束。这意味着当逻辑设计旨在在UPLD和MPLD之间进行迁移时，只能使用特征交集。为了便于迁移，可以创建成对的设备之间的固定映射。

9. 发明授权

US07530046B1 Chip debugging using incremental recompilation 有权
标题翻译：芯片调试使用增量重新编译
公开(公告)号：US07530046B1
公开(公告)日：2009-05-05
申请号：US11437285
申请日：2006-05-18
申请人： Gregor Nixon , Mark Jervis , Zhengjun Pan , Gihan De Silva , Steven Perry
发明人： Gregor Nixon , Mark Jervis , Zhengjun Pan , Gihan De Silva , Steven Perry
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5077
摘要： While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The technology-mapped netlist and placing and routing information corresponding to an original compiled design are saved into a database during full compilation. During debugging, an incremental compiler retrieves this information to build the original routing netlist. The database building, logic synthesis and technology mapping stages may be skipped. New connections are added, fitted to the device, and then the final routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD. The debugging assignments may be deleted.
摘要翻译：在调试时，用户选择增量重新编译。选择感兴趣的内部信号，并选择保留输出引脚。编译设计的增量重新编译包括从每个内部信号编译到输出引脚的路由。与原始编译设计对应的技术映射网表和放置和路由信息在完整编译期间保存到数据库中。在调试期间，增量编译器检索此信息以构建原始路由网表。可能会跳过数据库构建，逻辑综合和技术映射阶段。添加新的连接，安装到设备，然后最终路由网表以适合于编程PLD的形式输出到编程输出文件（POF）中。用户查看所选输出引脚上的内部信号。为了调试PLD，用户可以多次迭代此过程。调试分配可能会被删除。

10. 发明授权

US07360196B1 Technology mapping for programming and design of a programmable logic device by equating logic expressions 失效
标题翻译：通过等式逻辑表达式编程和设计可编程逻辑器件的技术映射
公开(公告)号：US07360196B1
公开(公告)日：2008-04-15
申请号：US10859842
申请日：2004-06-02
申请人： Steven Perry
发明人： Steven Perry
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A programmable logic device (“PLD”) architecture and a user logic design are modeled logically to find an efficient programming solution for the user logic design on the PLD architecture. The logical models are converted to equations—e.g., by representing them as binary decision diagrams which can be modeled and manipulated mathematically with commercially available tools. The equations can be solved for the programming or configuration variables. Similarly, an efficient programmable logic device architecture for implementing one or more of a given set of logic functions can be found by mapping each function in the set of functions onto a generic architecture and solving for the configuration variables. By comparing the results for all functions, one can reduce the generic architecture to an efficient architecture for that set of functions by eliminating structures from the generic architecture whose configuration bits are the same for all solutions.
摘要翻译：可编程逻辑器件（“PLD”）架构和用户逻辑设计被逻辑地建模，以便为PLD架构上的用户逻辑设计找到有效的编程解决方案。逻辑模型被转换为等式，例如，通过将它们表示为二进制决策图，其可以使用商业上可用的工具在数学上进行建模和操作。可以为编程或配置变量求解方程。类似地，用于实现给定逻辑功能集合中的一个或多个的有效的可编程逻辑器件架构可以通过将函数集合中的每个函数映射到通用架构并解决配置变量来找到。通过比较所有功能的结果，可以通过从通用体系结构中消除结构，将所有功能的配置位相同，从而将通用架构降低到该功能集的高效架构。

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