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1. 发明授权

US09748421B2 Multiple carbon nanotube transfer and its applications for making high-performance carbon nanotube field-effect transistor (CNFET), transparent electrodes, and three-dimensional integration of CNFETs 有权
公开(公告)号：US09748421B2
公开(公告)日：2017-08-29
申请号：US12718418
申请日：2010-03-05
申请人： Subhasish Mitra , Nishant P. Patil , Chung Chun Wan , H.-S. Philip Wong
发明人： Subhasish Mitra , Nishant P. Patil , Chung Chun Wan , H.-S. Philip Wong
IPC分类号： H01L31/0352 , B08B7/00 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L51/00 , H01L27/28 , H01L51/05
CPC分类号： H01L31/035281 , B08B7/0035 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L27/283 , H01L51/0013 , H01L51/003 , H01L51/0048 , H01L51/0541 , H01L51/0558 , Y02E10/549 , Y02P70/521
摘要： A wafer-scale multiple carbon nanotube transfer process is provided. According to one embodiment of the invention, plasma exposure processes are performed at various stages of the fabrication process of a carbon nanotube device or article to improve feasibility and yield for successive transfers of nanotubes. In one such carbon nanotube transfer process, a carrier material is partially etched by a plasma process before removing the carrier material through, for example, a wet etch. By applying the subject plasma exposure processes, fabrication of ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics is facilitated. The ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics fabricated utilizing embodiments of the invention can be used, for example, to make high-performance carbon nanotube field effect transistors (CNFETs) and low cost, highly-transparent, and low-resistivity electrodes for solar cell and flat panel display applications. Further, three-dimensional CNFETs can be provided by utilizing the subject plasma exposure processes.

2. 发明申请

US20060168489A1 System and shadow circuits with output joining circuit 有权
标题翻译：具有输出接合电路的系统和阴影电路
公开(公告)号：US20060168489A1
公开(公告)日：2006-07-27
申请号：US11044826
申请日：2005-01-26
申请人： Subhasish Mitra , Ming Zhang , Tak Mak , Quan Shi , Kee Kim
发明人： Subhasish Mitra , Ming Zhang , Tak Mak , Quan Shi , Kee Kim
IPC分类号： G01R31/28
CPC分类号： G01R31/318541
摘要： In one embodiment, an apparatus includes a system circuit adapted to generate at a first output terminal a first output signal in response to a data input signal and at least one system clock signal; a shadow circuit adapted to generate at a second output terminal a second output signal in response the data input signal and the at least one system clock signal; and an output joining circuit coupled to at least the first output terminal and the second output terminal.
摘要翻译：在一个实施例中，一种装置包括适于在第一输出端产生响应于数据输入信号和至少一个系统时钟信号的第一输出信号的系统电路; 阴影电路，其适于在第二输出端产生响应于所述数据输入信号和所述至少一个系统时钟信号的第二输出信号; 以及耦合到至少第一输出端子和第二输出端子的输出接合电路。

3. 发明申请

US20060168487A1 System pulse latch and shadow pulse latch coupled to output joining circuit 有权
标题翻译：系统脉冲锁存和阴影脉冲锁存器耦合到输出接合电路
公开(公告)号：US20060168487A1
公开(公告)日：2006-07-27
申请号：US11128692
申请日：2005-05-12
申请人： Tak Mak , Ming Zhang , Subhasish Mitra , Paul Shipley
发明人： Tak Mak , Ming Zhang , Subhasish Mitra , Paul Shipley
IPC分类号： G11B20/20 , G06K5/04 , G11B5/00
CPC分类号： H03K3/356156 , G01R31/318583 , H03K3/0375
摘要： In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a shadow pulse latch to generate at least one shadow latch signal in response to the data input signal and the pulsed system clock signal; and an output joining circuit, coupled to the system pulse latch and the shadow pulse latch, to provide a data output signal in response to the at least one system latch signal and the at least one shadow latch signal.
摘要翻译：在一个实施例中，一种装置包括系统脉冲锁存器，用于响应于数据输入信号和脉冲系统时钟信号而产生至少一个系统锁存信号; 阴影脉冲锁存器，用于响应于数据输入信号和脉冲系统时钟信号而产生至少一个阴影锁存信号; 以及耦合到系统脉冲锁存器和阴影脉冲锁存器的输出连接电路，以响应于至少一个系统锁存信号和至少一个阴影锁存信号来提供数据输出信号。

4. 发明授权

US08065634B1 System and method for analyzing a nanotube logic circuit 有权
标题翻译：用于分析纳米管逻辑电路的系统和方法
公开(公告)号：US08065634B1
公开(公告)日：2011-11-22
申请号：US12240409
申请日：2008-09-29
申请人： Nishant Patil , Subhasish Mitra
发明人： Nishant Patil , Subhasish Mitra
IPC分类号： G06F17/50
CPC分类号： B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0558
摘要： A method for validating a nanotube logic network. The nanotube logic network is separated into regions based on a conductivity of the respective region. Potential paths through adjoining regions of the nanotube logic network are determined. Boolean path functions for each potential path are determined. If the Boolean path functions of the potential paths are equivalent to the intended logic function, then the nanotube logic network is immune to misaligned carbon nanotubes.
摘要翻译：一种验证纳米管逻辑网络的方法。基于相应区域的导电性，将纳米管逻辑网络分成多个区域。确定了通过纳米管逻辑网络的邻接区域的潜在路径。确定每个潜在路径的布尔路径函数。如果潜在路径的布尔路径函数等同于预期的逻辑函数，则纳米管逻辑网络对不对准的碳纳米管是免疫的。

5. 发明申请

US20110133284A1 MULTIPLE CARBON NANOTUBE TRANSFER AND ITS APPLICATIONS FOR MAKING HIGH-PERFORMANCE CARBON NANOTUBE FIELD-EFFECT TRANSISTOR (CNFET), TRANSPARENT ELECTRODES, AND THREE-DIMENSIONAL INTEGRATION OF CNFETS 有权
标题翻译：多碳纳米管转移及其制备高性能碳纳米管场效应晶体管（CNFET），透明电极和CNFET的三维集成的应用
公开(公告)号：US20110133284A1
公开(公告)日：2011-06-09
申请号：US12718418
申请日：2010-03-05
申请人： SUBHASISH MITRA , Nishant P. Patil , Chung Chun Wan , H.-S. Philip Wong
发明人： SUBHASISH MITRA , Nishant P. Patil , Chung Chun Wan , H.-S. Philip Wong
IPC分类号： H01L27/088 , B08B7/00 , H01B13/00 , B32B38/00 , H01L21/302 , B82Y40/00 , B82Y99/00
CPC分类号： H01L31/035281 , B08B7/0035 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L27/283 , H01L51/0013 , H01L51/003 , H01L51/0048 , H01L51/0541 , H01L51/0558 , Y02E10/549 , Y02P70/521
摘要： A wafer-scale multiple carbon nanotube transfer process is provided. According to one embodiment of the invention, plasma exposure processes are performed at various stages of the fabrication process of a carbon nanotube device or article to improve feasibility and yield for successive transfers of nanotubes. In one such carbon nanotube transfer process, a carrier material is partially etched by a plasma process before removing the carrier material through, for example, a wet etch. By applying the subject plasma exposure processes, fabrication of ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics is facilitated. The ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics fabricated utilizing embodiments of the invention can be used, for example, to make high-performance carbon nanotube field effect transistors (CNFETs) and low cost, highly-transparent, and low-resistivity electrodes for solar cell and flat panel display applications. Further, three-dimensional CNFETs can be provided by utilizing the subject plasma exposure processes.
摘要翻译：提供了晶圆级多碳纳米管转移工艺。根据本发明的一个实施方案，等离子体暴露过程在碳纳米管装置或制品的制造过程的各个阶段进行，以提高连续转移纳米管的可行性和产率。在一种这样的碳纳米管转移方法中，通过例如湿蚀刻除去载体材料之前，通过等离子体工艺部分地蚀刻载体材料。通过应用目标等离子体曝光工艺，便于制造超高密度纳米管和超高密度纳米管网格或织物。使用本发明实施例制造的超高密度纳米管和超高密度纳米管网格或织物可用于例如制造高性能碳纳米管场效应晶体管（CNFET）和低成本，高透明度，以及用于太阳能电池和平板显示器应用的低电阻率电极。此外，可以通过利用目标等离子体曝光工艺来提供三维CNFET。

6. 发明授权

US07523371B2 System and shadow bistable circuits coupled to output joining circuit 失效
标题翻译：耦合到输出接合电路的系统和阴影双稳态电路
公开(公告)号：US07523371B2
公开(公告)日：2009-04-21
申请号：US11218979
申请日：2005-09-02
申请人： Subhasish Mitra , Ming Zhang , Kee Sup Kim
发明人： Subhasish Mitra , Ming Zhang , Kee Sup Kim
IPC分类号： G01R31/28 , G06F7/02 , G06F13/00
CPC分类号： G01R31/318536 , G01R31/318525
摘要： In one embodiment, an apparatus is provide with a combinational logic circuit to generate a data input signal; a delay element, coupled to the combinational logic circuit, to provide a delayed data input signal in response to the data input signal. Additionally, the apparatus is provided with a system bistable circuit, coupled to the combinational logic circuit, to generate a system bistable signal in response to at least the data input signal; a shadow bistable circuit, coupled to the delay element, to generate a shadow bistable signal in response to at least the delayed data input signal. Further, the apparatus is provided with an output joining circuit, coupled to the system and the shadow bistable circuits, to provide a data output signal in response to the system and the shadow bistable signals.
摘要翻译：在一个实施例中，设备提供组合逻辑电路以产生数据输入信号; 耦合到组合逻辑电路的延迟元件，以响应于数据输入信号提供延迟的数据输入信号。另外，该装置设置有耦合到组合逻辑电路的系统双稳态电路，以响应于至少数据输入信号产生系统双稳态信号; 耦合到延迟元件的阴影双稳态电路，以响应于至少延迟的数据输入信号产生阴影双稳态信号。此外，该装置设置有耦合到系统和阴影双稳态电路的输出接合电路，以响应于系统和阴影双稳态信号提供数据输出信号。

7. 发明授权

US07409631B2 Error-detection flip-flop 有权
标题翻译：错误检测触发器
公开(公告)号：US07409631B2
公开(公告)日：2008-08-05
申请号：US11323675
申请日：2005-12-30
申请人： James Tschanz , Subhasish Mitra , Vivek De
发明人： James Tschanz , Subhasish Mitra , Vivek De
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G01R31/31937 , G01R31/31726
摘要： An error-detection flip-flop is disclosed for identifying timing errors in digital circuits. The error-detection flip-flop is a master-slave flip-flop including logic to determine whether an input signal is received during a predetermined clock period, signifying a timing error. The error-detection flip-flop produces a variable-length error pulse, which may be combined with other error pulses and converted to a stable signal for sampling by error-correction circuitry. The error-detection flip-flop does not increase the clocking power of the digital circuit and consumes little additional circuit area.
摘要翻译：公开了用于识别数字电路中的定时误差的错误检测触发器。误差检测触发器是主从触发器，其包括用于确定在预定时钟周期期间是否接收到输入信号的逻辑，表示定时误差。误差检测触发器产生可变长度误差脉冲，其可以与其他误差脉冲组合并转换成用于由纠错电路进行采样的稳定信号。误差检测触发器不会增加数字电路的时钟功率，并且消耗少量额外的电路面积。

8. 发明授权

US07188284B2 Error detecting circuit 失效
标题翻译：错误检测电路
公开(公告)号：US07188284B2
公开(公告)日：2007-03-06
申请号：US10882523
申请日：2004-06-30
申请人： Subhasish Mitra , Kee S. Kim , Tak M. Mak , Prashant M. Goteti
发明人： Subhasish Mitra , Kee S. Kim , Tak M. Mak , Prashant M. Goteti
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/31816 , G01R31/318566 , G11C2029/3202
摘要： In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation; and an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.
摘要翻译：在一个实施例中，一种装置包括数据路径电路，用于响应于数据输入信号和至少第一数据时钟信号而产生数据输出信号; 阴影电路，耦合到数据路径电路，以在功能操作模式期间响应于数据输入信号和至少第二数据时钟信号产生阴影输出信号，并且响应于扫描信号产生扫描输出信号，在测试操作模式期间的信号和至少第一测试时钟信号; 以及耦合到数据路径和阴影电路的误差检测电路，以响应于数据输出信号和阴影输出信号之间的失配而产生误差信号。

9. 发明申请

US20060005103A1 System and scanout circuits with error resilience circuit 失效
标题翻译：具有错误恢复电路的系统和扫描电路
公开(公告)号：US20060005103A1
公开(公告)日：2006-01-05
申请号：US11050996
申请日：2005-02-04
申请人： Ming Zhang , Subhasish Mitra , Tak Mak , Victor Zia
发明人： Ming Zhang , Subhasish Mitra , Tak Mak , Victor Zia
IPC分类号： G01R31/28 , H03M13/00
CPC分类号： G01R31/318566 , G01R31/31816 , G01R31/318541 , G01R31/318572 , G11C2029/3202
摘要： In one embodiment, an apparatus is provided with a system circuit, a scanout circuit and an error detecting circuit. The system circuit is adapted to generate a first output signal in response to a data input signal and a system clock signal. The scanout circuit is adapted to generate a second output signal in response the data input signal and the system clock signal. The error detecting circuit, coupled to the system circuit and the scanout circuit, is adapted to generate an error signal in response to a relative condition between the first output signal and the second output signal.
摘要翻译：在一个实施例中，设备具有系统电路，扫描输出电路和错误检测电路。系统电路适于响应于数据输入信号和系统时钟信号产生第一输出信号。扫描输出电路适于响应于数据输入信号和系统时钟信号产生第二输出信号。耦合到系统电路和扫描输出电路的误差检测电路适于响应于第一输出信号和第二输出信号之间的相对条件产生误差信号。

10. 发明申请

US20060005091A1 Error detecting circuit 失效
标题翻译：错误检测电路
公开(公告)号：US20060005091A1
公开(公告)日：2006-01-05
申请号：US10882523
申请日：2004-06-30
申请人： Subhasish Mitra , Kee Kim , Tak Mak , Prashant Goteti
发明人： Subhasish Mitra , Kee Kim , Tak Mak , Prashant Goteti
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/31816 , G01R31/318566 , G11C2029/3202
摘要： In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation; and an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.
摘要翻译：在一个实施例中，一种装置包括数据路径电路，用于响应于数据输入信号和至少第一数据时钟信号而产生数据输出信号; 阴影电路，耦合到数据路径电路，以在功能操作模式期间响应于数据输入信号和至少第二数据时钟信号产生阴影输出信号，并且响应于扫描信号产生扫描输出信号，在测试操作模式期间的信号和至少第一测试时钟信号; 以及耦合到数据路径和阴影电路的误差检测电路，以响应于数据输出信号和阴影输出信号之间的失配而产生误差信号。

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