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1. 发明申请

US20090010079A1 One-transistor type dram 失效
公开(公告)号：US20090010079A1
公开(公告)日：2009-01-08
申请号：US12003923
申请日：2008-01-03
申请人： Hee Bok Kang , Jin Hong An , Sung Joo Hong , Suk Kyoung Hong
发明人： Hee Bok Kang , Jin Hong An , Sung Joo Hong , Suk Kyoung Hong
IPC分类号： G11C5/14
CPC分类号： G11C11/404 , G11C11/4091 , G11C11/4096 , G11C11/4099 , G11C2211/4016
摘要： A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages.

2. 发明授权

US07864611B2 One-transistor type DRAM 失效
标题翻译：单晶体管型DRAM
公开(公告)号：US07864611B2
公开(公告)日：2011-01-04
申请号：US12609649
申请日：2009-10-30
申请人： Hee Bok Kang , Jin Hong An , Sung Joo Hong , Suk Kyoung Hong
发明人： Hee Bok Kang , Jin Hong An , Sung Joo Hong , Suk Kyoung Hong
IPC分类号： G11C7/02
CPC分类号： G11C11/404 , G11C11/4091 , G11C11/4096 , G11C11/4099 , G11C2211/4016
摘要： A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages.
摘要翻译：单晶体管型DRAM包括连接在位线和源极线之间并由字线控制的浮体存储元件。 DRAM包括沿行方向布置的多个源极线和字线，沿列方向布置的多个位线，沿列方向布置的多个参考位线，包括浮体存储元件的单元阵列和形成在源极线，字线和位线交叉的区域中，形成在源极线，字线和位线交叉配置的区域中的包括浮体存储元件的基准单元阵列输出具有多个电平的参考电流;多个参考电压产生单元，连接到参考位线并被配置为产生与具有多个电平的参考电流相对应的多个参考电压;以及读出放大器和写入驱动单元连接到位线并被配置为接收多个参考电压。

3. 发明授权

US07630262B2 One-transistor type dram 失效
标题翻译：单晶体管式
公开(公告)号：US07630262B2
公开(公告)日：2009-12-08
申请号：US12003923
申请日：2008-01-03
申请人： Hee Bok Kang , Jin Hong An , Sung Joo Hong , Suk Kyoung Hong
发明人： Hee Bok Kang , Jin Hong An , Sung Joo Hong , Suk Kyoung Hong
IPC分类号： G11C7/02
CPC分类号： G11C11/404 , G11C11/4091 , G11C11/4096 , G11C11/4099 , G11C2211/4016
摘要： A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages.
摘要翻译：单晶体管型DRAM包括连接在位线和源极线之间并由字线控制的浮体存储元件。 DRAM包括沿行方向布置的多个源极线和字线，沿列方向布置的多个位线，沿列方向布置的多个参考位线，包括浮体存储元件的单元阵列和形成在源极线，字线和位线交叉的区域中，形成在源极线，字线和位线交叉配置的区域中的包括浮体存储元件的基准单元阵列输出具有多个电平的参考电流;多个参考电压产生单元，连接到参考位线并被配置为产生与具有多个电平的参考电流相对应的多个参考电压;以及读出放大器和写入驱动单元连接到位线并被配置为接收多个参考电压。

4. 发明申请

US20100046308A1 ONE-TRANSISTOR TYPE DRAM 失效
标题翻译：单晶体型DRAM
公开(公告)号：US20100046308A1
公开(公告)日：2010-02-25
申请号：US12609649
申请日：2009-10-30
申请人： Hee Bok KANG , Jin Hong An , Sung Joo Hong , Suk Kyoung Hong
发明人： Hee Bok KANG , Jin Hong An , Sung Joo Hong , Suk Kyoung Hong
IPC分类号： G11C5/14 , G11C7/02
CPC分类号： G11C11/404 , G11C11/4091 , G11C11/4096 , G11C11/4099 , G11C2211/4016
摘要： A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages.
摘要翻译：单晶体管型DRAM包括连接在位线和源极线之间并由字线控制的浮体存储元件。 DRAM包括沿行方向布置的多个源极线和字线，沿列方向布置的多个位线，沿列方向布置的多个参考位线，包括浮体存储元件的单元阵列和形成在源极线，字线和位线交叉的区域中，形成在源极线，字线和位线交叉配置的区域中的包括浮体存储元件的基准单元阵列输出具有多个电平的参考电流;多个参考电压产生单元，连接到参考位线并被配置为产生与具有多个电平的参考电流对应的多个参考电压;以及读出放大器和写入驱动单元连接到位线并被配置为接收多个参考电压。

5. 发明授权

US08325541B2 Non-volatile semiconductor memory apparatus 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US08325541B2
公开(公告)日：2012-12-04
申请号：US12346646
申请日：2008-12-30
申请人： Tae Su Jang , Sung Joo Hong , Sung Woong Chung
发明人： Tae Su Jang , Sung Joo Hong , Sung Woong Chung
IPC分类号： G11C7/00
CPC分类号： G11C11/404 , G11C8/10 , G11C11/005 , G11C13/0004 , G11C2211/4016
摘要： A non-volatile semiconductor memory apparatus includes a first memory area configured to include a plurality of non-volatile memory cells, a second memory area configured to include a plurality of memory cells whose write speed is faster than the plurality of non-volatile memory cells, and a host interface configured to control the first and second memory areas, wherein the first and second memory areas are configured to be provided with the same address signal and command signal from the host interface.
摘要翻译：一种非易失性半导体存储装置，包括被配置为包括多个非易失性存储单元的第一存储区域，第二存储区域，被配置为包括写入速度比多个非易失性存储单元更快的多个存储单元以及被配置为控制第一和第二存储器区域的主机接口，其中第一和第二存储器区域被配置为从主机接口提供相同的地址信号和命令信号。

6. 发明申请

US20100091579A1 NON-VOLATILE SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100091579A1
公开(公告)日：2010-04-15
申请号：US12346646
申请日：2008-12-30
申请人： Tae Su Jang , Sung Joo Hong , Sung Woong Chung
发明人： Tae Su Jang , Sung Joo Hong , Sung Woong Chung
IPC分类号： G11C7/00
CPC分类号： G11C11/404 , G11C8/10 , G11C11/005 , G11C13/0004 , G11C2211/4016
摘要： A non-volatile semiconductor memory apparatus includes a first memory area configured to include a plurality of non-volatile memory cells, a second memory area configured to include a plurality of memory cells whose write speed is faster than the plurality of non-volatile memory cells, and a host interface configured to control the first and second memory areas, wherein the first and second memory areas are configured to be provided with the same address signal and command signal from the host interface.
摘要翻译：一种非易失性半导体存储装置，包括被配置为包括多个非易失性存储单元的第一存储区域，第二存储区域，被配置为包括写入速度比多个非易失性存储单元更快的多个存储单元以及被配置为控制第一和第二存储器区域的主机接口，其中第一和第二存储器区域被配置为从主机接口提供相同的地址信号和命令信号。

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