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    • 4. 发明授权
    • Ceramic chip assembly
    • 陶瓷芯片组装
    • US08599539B2
    • 2013-12-03
    • US13193836
    • 2011-07-29
    • Sun-Ki KimSeong-Jin LeeKi-Han Park
    • Sun-Ki KimSeong-Jin LeeKi-Han Park
    • H05K7/00H05K3/10
    • G01K7/16G01K1/08H01C1/028H01C7/008H01G2/103H01G4/224H01G4/236H01L2924/0002H01L2924/00
    • Provided is a ceramic chip assembly configured to economically and reliably insulate an exposed portion of a metal lead wire from an environmental change. The ceramic chip assembly includes a ceramic base having electrical characteristics, a pair of external electrodes that are disposed on a pair of surfaces of the ceramic base, respectively, the surfaces of the ceramic base being opposed to each other, a pair of metal lead wires as single cores having first ends that are electrically and mechanically connected to the external electrodes, respectively, by an electrical conductive adhesive member, an insulation sealant sealing the ceramic base, the external electrodes, and the first ends of the metal lead wires to expose second ends of the metal lead wires, and an insulation polymer coating layer continuously formed on both the insulation sealant and portions of the metal lead wires exposed out of the insulation sealant.
    • 提供了一种陶瓷芯片组件,其被配置为经济地且可靠地将金属引线的暴露部分与环境变化绝缘。 陶瓷芯片组件包括具有电特性的陶瓷基体,分别设置在陶瓷基体的一对表面上的一对外部电极,陶瓷基体的彼此相对的表面,一对金属引线 作为具有分别通过导电性粘接部件,绝缘密封剂密封陶瓷基体,外部电极以及金属引线的第一端部的绝缘密封材料而分别与外部电极电连接和机械连接的第一端的单芯 金属引线的端部和连续地形成在绝缘密封剂和从绝缘密封剂露出的金属引线的部分上的绝缘聚合物涂层。
    • 10. 发明授权
    • Method for testing standby current of semiconductor package
    • 半导体封装待机电流测试方法
    • US07368933B2
    • 2008-05-06
    • US11335270
    • 2006-01-18
    • Moon-Bo SimJoo-Seok KwakSeong-Su KimYun-Bo YangSun-Ki Kim
    • Moon-Bo SimJoo-Seok KwakSeong-Su KimYun-Bo YangSun-Ki Kim
    • G01R31/01G01R31/28G01R31/26
    • G01R31/3008
    • A system and method for testing standby current of a semiconductor package is provided. The method includes testing semiconductor chips formed on a wafer having a predetermined wafer run number, collecting measured values of standby current of the semiconductor chips, and storing the measured values of standby current in a database, by using a wafer tester; recognizing a wafer run number of each of semiconductor packages to be tested; downloading measured values of standby current of semiconductor chips corresponding to the recognized wafer run number from the database to a semiconductor package tester; extracting a boundary value defining predetermined upper values of the downloaded measured values of standby current, by using the semiconductor package tester; setting the boundary value as a standby current limit of a program for testing the semiconductor packages by use of the semiconductor package tester; and testing the semiconductor packages based on the standby current limit.
    • 提供一种用于测试半导体封装的待机电流的系统和方法。 该方法包括测试形成在具有预定晶圆行程号的晶片上的半导体芯片,收集半导体芯片的待机电流的测量值,并通过使用晶片测试器将待机电流的测量值存储在数据库中; 识别要测试的每个半导体封装的晶片运行次数; 将与识别的晶片运行数相对应的半导体芯片的待机电流的测量值从数据库下载到半导体封装测试器; 通过使用半导体封装测试器提取定义下载的待机电流测量值的预定上限值的边界值; 将边界值设置为通过使用半导体封装测试器来测试半导体封装的程序的备用电流极限; 并根据待机电流限制测试半导体封装。