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1. 发明授权

US08499021B2 Circuit and method for computing circular convolution in streaming mode 失效
标题翻译：在流模式下计算循环卷积的电路和方法
公开(公告)号：US08499021B2
公开(公告)日：2013-07-30
申请号：US12868102
申请日：2010-08-25
申请人： Tadeusz Jarosinski
发明人： Tadeusz Jarosinski
IPC分类号： G06F17/15
CPC分类号： G06F17/15 , H03H17/0213
摘要： A circuit and method for computing the circular convolution of an input signal with a finite impulse response operates to store initial input samples of the input signal, perform convolution of the remaining input samples in the block of input samples and then supplying the stored initial input samples for convolution, thereby generating circular convolution output samples.
摘要翻译：用于计算具有有限脉冲响应的输入信号的循环卷积的电路和方法用于存储输入信号的初始输入样本，执行输入样本块中剩余输入样本的卷积，然后提供所存储的初始输入样本用于卷积，从而产生循环卷积输出样本。

2. 发明申请

US20100285744A1 GAIN CONTROL METRIC COMPUTATION IN A WIRELESS REPEATER 有权
标题翻译：在无线重发器中增益控制公制计算
公开(公告)号：US20100285744A1
公开(公告)日：2010-11-11
申请号：US12722733
申请日：2010-03-12
申请人： Michael Mao Wang , Dhananjay Ashok Gore , Tadeusz Jarosinski
发明人： Michael Mao Wang , Dhananjay Ashok Gore , Tadeusz Jarosinski
IPC分类号： H04B7/14
CPC分类号： H04B7/15578
摘要： A method for computing a gain control metric used in controlling gain in a wireless repeater operates to store correlation and normalization values associated with the gain control metric for the previous N samples in registers. For each new sample of the gain control input signal, the correlation and normalization values are computed by discarding the multiplication terms of the obsolete sample and adding the multiplication terms of the new sample to the stored correlation and normalization values. In this manner, the complexity of the computation is greatly reduced and the complexity of the computation does not increase with the integration length.
摘要翻译：用于计算用于控制无线中继器中的增益的增益控制度量的方法用于存储与寄存器中先前N个采样的增益控制度量相关联的相关和归一化值。对于增益控制输入信号的每个新样本，通过舍弃过时采样的乘法项和将新采样的乘法项加到存储的相关和归一化值来计算相关和归一化值。以这种方式，大大降低了计算的复杂度，并且计算的复杂度不会随着积分长度而增加。

3. 发明申请

US20080005366A1 Apparatus and methods for handling requests over an interface 审中-公开
标题翻译：通过接口处理请求的装置和方法
公开(公告)号：US20080005366A1
公开(公告)日：2008-01-03
申请号：US11398157
申请日：2006-04-04
申请人： Sreenidhi Raatni , Tadeusz Jarosinski
发明人： Sreenidhi Raatni , Tadeusz Jarosinski
IPC分类号： G06F3/00
CPC分类号： G06F13/36 , G06F13/24 , G06F13/385 , H04W24/02
摘要： Apparatus and methods for an interface are disclosed. In particular, an apparatus for handling hardware requests over an interface between a hardware circuit and another circuit, such as a radio frequency integrated circuit (RFIC) is disclosed. The hardware request controller apparatus utilizes a configuration memory that receives and stores data concerning memory address locations within a data memory, also within the controller. The data memory receives and stores read or write data used for reading data from and writing data to the other circuit. The controller apparatus also includes master state machine logic that receives the hardware request commands from the hardware circuit and determines which address locations are to be accessed in the data memory based on the data concerning memory locations stored in the configuration memory. An interface dependent logic, adapted to the particular interface bus, is also provided to transfer read out data from the data memory to the other circuit via an interface bus. Corresponding methods are also disclosed.
摘要翻译：公开了用于接口的装置和方法。具体地，公开了一种用于通过硬件电路和另一电路（诸如射频集成电路（RFIC））之间的接口处理硬件请求的装置。硬件请求控制器装置利用配置存储器，该配置存储器还接收并存储与数据存储器内的存储器地址位置有关的数据，也在控制器内。数据存储器接收并存储用于从另一电路读取数据和将数据写入另一电路的读或写数据。控制器装置还包括主状态机逻辑，其基于与存储在配置存储器中的存储器位置有关的数据，从硬件电路接收硬件请求命令并确定哪些地址位置将被存储在数据存储器中。还提供了适用于特定接口总线的接口相关逻辑，用于经由接口总线将数据从数据存储器传送到另一电路。还公开了相应的方法。

4. 发明申请

US20070271571A1 Apparatus and methods for discriminating late software commands sent to hardware 失效
标题翻译：用于识别发送到硬件的较晚软件命令的装置和方法
公开(公告)号：US20070271571A1
公开(公告)日：2007-11-22
申请号：US11398061
申请日：2006-04-04
申请人： Tadeusz Jarosinski
发明人： Tadeusz Jarosinski
IPC分类号： G06F9/46
CPC分类号： G06F9/545
摘要： Apparatus and methods for discriminating late software commands sent to hardware from software executed by a processor. The apparatus, in particular, includes a storage device configured to receive information concerning a timing requirement for software commands transmitted from a microprocessor, where the timing requirement is dependent on a system time. A time counter is also included and configured to determine the system time. The apparatus further includes a comparator configured to determine whether the timing requirement has been met, and a switching circuit configured to selectively allow the software command to be issued from the processor to a hardware circuit based on the determination of whether the timing requirement has been met. Complementary methods are also disclosed.
摘要翻译：用于鉴别由处理器执行的软件发送到硬件的晚期软件命令的装置和方法。该装置具体包括存储装置，其被配置为接收关于从微处理器发送的软件命令的定时要求的信息，其中定时要求取决于系统时间。时间计数器也被包括并配置为确定系统时间。该装置还包括比较器，其被配置为确定是否满足了定时要求，以及切换电路，被配置为基于是否已经满足了定时要求的确定来选择性地允许从处理器向硬件电路发出软件命令。还公开了互补方法。

5. 发明授权

US08380122B2 Signal blanking for improved frequency domain channel estimation 有权
标题翻译：信号消隐用于改进频域信道估计
公开(公告)号：US08380122B2
公开(公告)日：2013-02-19
申请号：US12708318
申请日：2010-02-18
申请人： Steven J. Howard , Tadeusz Jarosinski , Dhananjay Ashok Gore , Gwendolyn Denise Barriac , Michael Mao Wang , Tao Tian
发明人： Steven J. Howard , Tadeusz Jarosinski , Dhananjay Ashok Gore , Gwendolyn Denise Barriac , Michael Mao Wang , Tao Tian
IPC分类号： H04B3/36 , H04B7/14
CPC分类号： H04B7/15535 , H04B7/15585 , H04L27/2607 , H04L27/2613
摘要： A wireless repeater includes a channel estimation block to estimate a feedback channel between the antennas of the repeater using frequency domain channel estimation. The repeater includes a pilot signal blanking circuit to blank out a selected number of samples of the pilot signal to improve the accuracy of the channel estimation. In another embodiment, the repeater replaces T samples of the pilot signal with a cyclic prefix.
摘要翻译：无线中继器包括信道估计块，用于使用频域信道估计来估计中继器的天线之间的反馈信道。中继器包括导频信号消隐电路，用于消除导频信号的选定数目的样本，以提高信道估计的精度。在另一个实施例中，中继器用循环前缀替换导频信号的T个样本。

6. 发明申请

US20120051406A1 CIRCUIT AND METHOD FOR COMPUTING CIRCULAR CONVOLUTION IN STREAMING MODE 失效
标题翻译：在流动模式下计算循环流量的电路和方法
公开(公告)号：US20120051406A1
公开(公告)日：2012-03-01
申请号：US12868102
申请日：2010-08-25
申请人： TADEUSZ JAROSINSKI
发明人： TADEUSZ JAROSINSKI
IPC分类号： H04L25/60 , H04L27/06 , H04L27/28
CPC分类号： G06F17/15 , H03H17/0213
摘要： A circuit and method for computing the circular convolution of an input signal with a finite impulse response operates to store initial input samples of the input signal, perform convolution of the remaining input samples in the block of input samples and then supplying the stored initial input samples for convolution, thereby generating circular convolution output samples.
摘要翻译：用于计算具有有限脉冲响应的输入信号的循环卷积的电路和方法用于存储输入信号的初始输入样本，执行输入样本块中剩余输入样本的卷积，然后提供所存储的初始输入样本用于卷积，从而产生循环卷积输出样本。

7. 发明授权

US07661009B2 Apparatus and methods for discriminating late software commands sent to hardware 失效
标题翻译：用于识别发送到硬件的较晚软件命令的装置和方法
公开(公告)号：US07661009B2
公开(公告)日：2010-02-09
申请号：US11398061
申请日：2006-04-04
申请人： Tadeusz Jarosinski
发明人： Tadeusz Jarosinski
IPC分类号： G06F1/00 , G06F1/14 , G06F19/00
CPC分类号： G06F9/545
摘要： Apparatus and methods for discriminating late software commands sent to hardware from software executed by a processor. The apparatus, in particular, includes a storage device configured to receive information concerning a timing requirement for software commands transmitted from a microprocessor, where the timing requirement is dependent on a system time. A time counter is also included and configured to determine the system time. The apparatus further includes a comparator configured to determine whether the timing requirement has been met, and a switching circuit configured to selectively allow the software command to be issued from the processor to a hardware circuit based on the determination of whether the timing requirement has been met. Complementary methods are also disclosed.
摘要翻译：用于鉴别由处理器执行的软件发送到硬件的晚期软件命令的装置和方法。该装置具体包括存储装置，其被配置为接收关于从微处理器发送的软件命令的定时要求的信息，其中定时要求取决于系统时间。时间计数器也被包括并配置为确定系统时间。该装置还包括比较器，其被配置为确定是否满足了定时要求，以及切换电路，被配置为基于是否已经满足了定时要求的确定来选择性地允许从处理器向硬件电路发出软件命令。还公开了互补方法。

8. 发明申请

US20060240798A1 Apparatus and methods for control of sleep modes in a transceiver 有权
公开(公告)号：US20060240798A1
公开(公告)日：2006-10-26
申请号：US11372876
申请日：2006-03-10
申请人： Tadeusz Jarosinski , Chinnappa Ganapathy , Michael Wang
发明人： Tadeusz Jarosinski , Chinnappa Ganapathy , Michael Wang
IPC分类号： H04B1/16 , H04B1/38 , H04M1/00
CPC分类号： H04W52/0225 , H04B1/1615 , H04W52/0293 , Y02D70/1222 , Y02D70/1242 , Y02D70/164 , Y02D70/40
摘要： Disclosed are apparatus and methods for control of sleep modes in a transceiver or receiver. In particular, a transceiver is disclosed including a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver. The transceiver also includes a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.

9. 发明授权

US08041972B2 Apparatus and method for setting wakeup times in a communication device based on estimated lock on time of frequency synthesizer 有权
标题翻译：基于估计的频率合成器的锁定时间在通信设备中设置唤醒时间的装置和方法
公开(公告)号：US08041972B2
公开(公告)日：2011-10-18
申请号：US11695442
申请日：2007-04-02
申请人： Tadeusz Jarosinski , Sreenidhi Raatni
发明人： Tadeusz Jarosinski , Sreenidhi Raatni
IPC分类号： G06F1/32
CPC分类号： H04W52/0283 , Y02D70/00
摘要： Apparatus and methods for setting wakeup times in a communication device are disclosed where setting the wakeup times includes estimating the lock on time of a frequency synthesizer in order to minimize the wakeup time and extend sleep times for maximal energy savings. A disclosed apparatus includes an estimator to receive a current lock on time of a frequency synthesizer, which is the time taken by the frequency synthesizer to lock on to particular frequency after a wakeup signal has been issued to turn on the synthesizer after a sleep period. The estimator calculates a latest estimated lock on time based at least on the current lock on time of the frequency synthesizer and determines an enable signal timing information based on the estimated lock on time. The apparatus also includes a timer configured to receive the enable signal timing information and issue at least one enable signal to turn on other circuitry in the transceiver after the synthesizer lock on period based thereon. Corresponding methods are also disclosed.
摘要翻译：公开了在通信设备中设置唤醒时间的装置和方法，其中设置唤醒时间包括估计频率合成器的锁定时间，以便最小化唤醒时间并延长睡眠时间以实现最大的能量节省。所公开的装置包括估计器，用于接收频率合成器的当前锁定时间，频率合成器是在唤醒信号已经被发出以在睡眠周期之后接通合成器时锁定到特定频率所花费的时间。估计器至少基于频率合成器的当前锁定时间来计算最新的估计锁定时间，并且基于估计的锁定时间确定使能信号定时信息。该装置还包括定时器，其被配置为接收使能信号定时信息，并且在合成器锁定基于周期的基础上发出至少一个使能信号以接通收发器中的其他电路。还公开了相应的方法。

10. 发明申请

US20100285738A1 SIGNAL BLANKING FOR IMPROVED FREQUENCY DOMAIN CHANNEL ESTIMATION 有权
标题翻译：用于改进的频域信道估计的信号空白
公开(公告)号：US20100285738A1
公开(公告)日：2010-11-11
申请号：US12708318
申请日：2010-02-18
申请人： Steven J. Howard , Tadeusz Jarosinski , Dhananjay Ashok Gore , Gwendolyn Denise Barriac , Michael Mao Wang , Tao Tian
发明人： Steven J. Howard , Tadeusz Jarosinski , Dhananjay Ashok Gore , Gwendolyn Denise Barriac , Michael Mao Wang , Tao Tian
IPC分类号： H04B17/02
CPC分类号： H04B7/15535 , H04B7/15585 , H04L27/2607 , H04L27/2613
摘要： A wireless repeater includes a channel estimation block to estimate a feedback channel between the antennas of the repeater using frequency domain channel estimation. The repeater includes a pilot signal blanking circuit to blank out a selected number of samples of the pilot signal to improve the accuracy of the channel estimation. In another embodiment, the repeater replaces T samples of the pilot signal with a cyclic prefix.
摘要翻译：无线中继器包括信道估计块，用于使用频域信道估计来估计中继器的天线之间的反馈信道。中继器包括导频信号消隐电路，用于消除导频信号的选定数目的样本，以提高信道估计的精度。在另一个实施例中，中继器用循环前缀替换导频信号的T个样本。

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