专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09136333B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09136333B2
公开(公告)日：2015-09-15
申请号：US13352415
申请日：2012-01-18
申请人： Takaaki Aoki , Tomofusa Shiga
发明人： Takaaki Aoki , Tomofusa Shiga
IPC分类号： H01L27/088 , H01L29/06 , H01L29/66 , H01L29/78 , H01L29/808 , H01L29/423
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66734 , H01L29/7803 , H01L29/7806 , H01L29/7811 , H01L29/7828 , H01L29/8083
摘要： A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.
摘要翻译：半导体器件包括：半导体衬底; 垂直型沟槽栅极MOS晶体管; 肖特基势垒二极管; 多个沟槽具有条纹图案以将内部区域分成第一和第二分离区域; 和每个沟槽中的多晶硅膜。第一分离区域包括用于提供源极的第一导电类型区域和用于提供沟道区域的第二导电类型层。第一导电类型区域与第一沟槽相邻。第一沟槽中的多晶硅膜与栅极布线耦合。第二沟槽不与第一导电类型区域相邻。第二沟槽中的多晶硅膜与源极或栅极布线耦合。第二分离区域中的衬底与用于提供肖特基势垒的源极配线耦合。

2. 发明授权

US08757237B2 Blind 有权
标题翻译：盲
公开(公告)号：US08757237B2
公开(公告)日：2014-06-24
申请号：US13639799
申请日：2011-03-23
申请人： Takaaki Aoki
发明人： Takaaki Aoki
IPC分类号： A47H1/00
CPC分类号： E06B9/262 , E06B9/322 , E06B2009/2452 , E06B2009/2622 , E06B2009/2625
摘要： In a blind with two shields, it is possible to perform different operations by operating one operating means and reduce the dimension of an operating device by reducing the number of parts. The operating device comprises an operating shaft rotated upon receiving an operation force, a clutch rotating integrally with the operating shaft and axially sliding on the operating shaft, and a first transmission member 50 and a second transmission member disposed at both axial sides of the clutch to transmit driving force to a first driving shaft and a second driving shaft, respectively. The sliding direction of the clutch is determined by the rotational direction of the operating shaft, such that as the clutch sliding on the operating shaft is engaged with one of the transmission members and, the rotation of the operating shaft is transmitted to any one of the driving shafts and through one of the transmission members and.
摘要翻译：在具有两个屏蔽的盲板中，可以通过操作一个操作装置来执行不同的操作，并且通过减少部件的数量来减小操作装置的尺寸。操作装置包括操作轴，其在接收到操作力时旋转，离合器与操作轴一体地旋转并在操作轴上轴向滑动;第一传动构件50和第二传动构件，其布置在离合器的两个轴向侧，分别向第一驱动轴和第二驱动轴传递驱动力。离合器的滑动方向由操作轴的旋转方向确定，使得当操作轴上的离合器滑动与传动构件中的一个接合时，操作轴的旋转被传递到驱动轴并通过传动构件之一和。

3. 发明授权

US08519748B2 Driving circuit for driving transistor based on control current 有权
标题翻译：基于控制电流驱动晶体管的驱动电路
公开(公告)号：US08519748B2
公开(公告)日：2013-08-27
申请号：US13433624
申请日：2012-03-29
申请人： Takaaki Aoki , Shoji Mizuno , Shigeki Takahashi , Takashi Nakano , Nozomu Akagi , Yoshiyuki Hattori , Makoto Kuwahara , Kyoko Okada
发明人： Takaaki Aoki , Shoji Mizuno , Shigeki Takahashi , Takashi Nakano , Nozomu Akagi , Yoshiyuki Hattori , Makoto Kuwahara , Kyoko Okada
IPC分类号： H03K3/00
CPC分类号： H01L27/0629 , H01L27/0255 , H03K17/063 , H03K17/165 , H03K17/168 , H03K17/567 , H03K17/687 , H03K2217/0036
摘要： A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a conduction state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector.
摘要翻译：开关电路包括：具有第一电极，第二电极和控制电极的晶体管; 齐纳二极管; 和电容器。通过切换晶体管的控制电压，第一电极和第二电极之间的连接能够在导通状态和非导通状态之间暂时切换。齐纳二极管和电容器串联耦合在晶体管的第一电极和控制电极之间。第一电极是漏极或集电极。

4. 发明授权

US08179169B2 Driving circuit with variable resistor for transistor 有权
标题翻译：具有晶体管可变电阻的驱动电路
公开(公告)号：US08179169B2
公开(公告)日：2012-05-15
申请号：US13105021
申请日：2011-05-11
申请人： Takaaki Aoki , Shoji Mizuno , Shigeki Takahashi , Takashi Nakano , Nozomu Akagi , Yoshiyuki Hattori , Makoto Kuwahara , Kyoko Okada
发明人： Takaaki Aoki , Shoji Mizuno , Shigeki Takahashi , Takashi Nakano , Nozomu Akagi , Yoshiyuki Hattori , Makoto Kuwahara , Kyoko Okada
IPC分类号： H03K3/00
CPC分类号： H01L27/0629 , H01L27/0255 , H03K17/063 , H03K17/165 , H03K17/168 , H03K17/567 , H03K17/687 , H03K2217/0036
摘要： A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a conduction state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector.
摘要翻译：开关电路包括：具有第一电极，第二电极和控制电极的晶体管; 齐纳二极管; 和电容器。通过切换晶体管的控制电压，第一电极和第二电极之间的连接能够在导通状态和非导通状态之间暂时切换。齐纳二极管和电容器串联耦合在晶体管的第一电极和控制电极之间。第一电极是漏极或集电极。

5. 发明申请

US20100102857A1 Switching circuit and driving circuit for transistor 有权
标题翻译：晶体管开关电路和驱动电路
公开(公告)号：US20100102857A1
公开(公告)日：2010-04-29
申请号：US12654323
申请日：2009-12-17
申请人： Takaaki Aoki , Shoji Mizuno , Shigeki Takahashi , Takashi Nakano , Nozomu Akagi , Yoshiyuki Hattori , Makoto Kuwahara , Kyoko Okada
发明人： Takaaki Aoki , Shoji Mizuno , Shigeki Takahashi , Takashi Nakano , Nozomu Akagi , Yoshiyuki Hattori , Makoto Kuwahara , Kyoko Okada
IPC分类号： H03K3/00 , H03K17/56
CPC分类号： H01L27/0629 , H01L27/0255 , H03K17/063 , H03K17/165 , H03K17/168 , H03K17/567 , H03K17/687 , H03K2217/0036
摘要： A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a condition state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector.
摘要翻译：开关电路包括：具有第一电极，第二电极和控制电极的晶体管; 齐纳二极管; 和电容器。第一电极和第二电极之间的连接能够通过切换晶体管的控制电压来暂时地在状态和非导通状态之间切换。齐纳二极管和电容器串联耦合在晶体管的第一电极和控制电极之间。第一电极是漏极或集电极。

6. 发明授权

US07563379B2 Dry etching method and photonic crystal device fabricated by use of the same 有权
标题翻译：干蚀刻法和使用其制造的光子晶体器件
公开(公告)号：US07563379B2
公开(公告)日：2009-07-21
申请号：US11008606
申请日：2004-12-08
申请人： Akiko Suzuki , Akinobu Sato , Emmanuel Bourelle , Jiro Matsuo , Toshio Seki , Takaaki Aoki
发明人： Akiko Suzuki , Akinobu Sato , Emmanuel Bourelle , Jiro Matsuo , Toshio Seki , Takaaki Aoki
IPC分类号： H01L21/302
CPC分类号： B82Y20/00 , B81C1/00531 , B81C1/00619 , G02B6/1225 , G02B6/136 , H01J2237/0812 , H01L21/3065
摘要： In a dry etching method in which clusters formed by agglomeration of atoms or molecules are ionized and accelerated as a cluster ion beam for irradiation of an object surface to etch away therefrom its constituent atoms, the clusters are mixed clusters 42 formed by agglomeration of two or more kinds of atoms or molecules, and the mixed clusters 42 contain atoms 43 of at least one of argon, neon, xenon and krypton, and a component 44 that is deposited on the object surface to form a thin film by reaction therewith. With this method, it is possible to provide an extremely reduced sidewall surface roughness and high vertical machining accuracy.
摘要翻译：在干法蚀刻方法中，通过原子或分子的聚集形成的团簇被离子化并加速作为用于照射物体表面的簇离子束以从其中去除其组成原子，所述簇是通过两个或多个更多种类的原子或分子，并且混合簇42包含氩，氖，氙和氪中的至少一种的原子43和沉积在物体表面上以通过与其反应形成薄膜的成分44。通过这种方法，可以提供极小的侧壁表面粗糙度和高垂直加工精度。

7. 发明授权

US06974996B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06974996B2
公开(公告)日：2005-12-13
申请号：US10726590
申请日：2003-12-04
申请人： Tomofusa Shiga , Takaaki Aoki , Yoshifumi Okabe
发明人： Tomofusa Shiga , Takaaki Aoki , Yoshifumi Okabe
IPC分类号： H01L21/28 , H01L21/331 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7813 , H01L21/28185 , H01L21/28194 , H01L29/42368 , H01L29/513 , H01L29/518 , H01L29/66348 , H01L29/7397 , Y10S257/90
摘要： In a semiconductor device having a trench-gate structure in which polysilicon doped with boron is embedded in a trench, insulating film formed on the inner wall of the trench comprises ONO film, and silicon nitride film constituting the ONO film is formed to such film thickness and film quality that boron can be suppressed from passing through the silicon nitride film. Silicon oxide film is formed so that a top oxide film is thin and a bottom oxide film is thick.
摘要翻译：在具有沟槽栅结构的半导体器件中，其中掺杂有硼的多晶硅嵌入在沟槽中，形成在沟槽内壁上的绝缘膜包括ONO膜，并且构成ONO膜的氮化硅膜形成为这样的膜厚度以及能够抑制硼通过氮化硅膜的膜质量。形成氧化硅膜，使得顶部氧化膜薄，底部氧化膜厚。

8. 发明授权

US06864532B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06864532B2
公开(公告)日：2005-03-08
申请号：US10175294
申请日：2002-06-20
申请人： Takaaki Aoki , Akira Kuroyanagi , Mikimasa Suzuki , Takafumi Arakawa , Yukio Tsuzuki
发明人： Takaaki Aoki , Akira Kuroyanagi , Mikimasa Suzuki , Takafumi Arakawa , Yukio Tsuzuki
IPC分类号： H01L21/28 , H01L21/331 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78 , H01L29/788
CPC分类号： H01L29/7813 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66348 , H01L29/7397
摘要： A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.
摘要翻译：沟槽栅型晶体管具有形成在沟槽的内壁上的栅极绝缘膜。栅极绝缘膜包括位于沟槽的壁上的第一部分和位于沟槽的上部和底部的第二部分。第一部分包括第一氧化膜，氮化物膜和第二氧化物膜。第二部分仅包括氧化膜并且比第一部分厚。因此，可以减小沟槽的上下角部的电场集中以提高耐压。此外，沟槽的端部可以具有比第一部分更厚的绝缘层。

9. 发明授权

US06797588B2 Method for manufacturing a semiconductor device having a trench and a thick insulation film at the trench opening 有权
标题翻译：在沟槽开口处制造具有沟槽和厚绝缘膜的半导体器件的方法
公开(公告)号：US06797588B2
公开(公告)日：2004-09-28
申请号：US10108443
申请日：2002-03-29
申请人： Eiji Ishikawa , Takaaki Aoki , Kenji Kondo
发明人： Eiji Ishikawa , Takaaki Aoki , Kenji Kondo
IPC分类号： H01L2176
CPC分类号： H01L29/7813 , H01L21/76235 , H01L21/823487 , H01L29/0657 , H01L29/42368 , H01L29/511 , H01L29/66348 , H01L29/7397
摘要： A surface of a semiconductor substrate is selectively etched to form a first opening, which serves as the opening of a trench. A USG film is deposited on the first opening. A second opening, the width of which is smaller than that of the first opening, is formed in the USG film within the first opening. An inner section of the trench is formed by etching while using the USG film as a mask. The inner surface of the inner region is thermally oxidized to form a silicon oxide film, and a gate insulating film is made by the silicon oxide film and the USG film. A gate electrode is formed in the trench. The gate insulating film is relatively thick at the opening of the trench, so the breakdown voltage at the opening of the trench is increased.
摘要翻译：选择性地蚀刻半导体衬底的表面以形成用作沟槽开口的第一开口。 USG胶片沉积在第一个开口处。在第一开口内的USG膜中形成第二开口，其宽度小于第一开口的宽度。在使用USG膜作为掩模的同时通过蚀刻形成沟槽的内部。内部区域的内表面被热氧化以形成氧化硅膜，并且通过氧化硅膜和USG膜制成栅极绝缘膜。在沟槽中形成栅电极。栅极绝缘膜在沟槽的开口处相对较厚，因此沟槽开口处的击穿电压增加。

10. 发明授权

US4001612A Linear resistance element for LSI circuitry 失效
标题翻译： LSI电路的线性电阻元件
公开(公告)号：US4001612A
公开(公告)日：1977-01-04
申请号：US641469
申请日：1975-12-17
申请人： Takaaki Aoki , Paul Evrenidis , Ryo Igarashi , Seiki Ogura
发明人： Takaaki Aoki , Paul Evrenidis , Ryo Igarashi , Seiki Ogura
IPC分类号： H01L27/04 , H01L21/822 , H01L27/088 , H01L29/78 , H01L27/02 , H01L29/66
CPC分类号： H01L27/088 , H01L29/78
摘要： This invention features the use of two paralleled insulated gate depletion channel field effect transistors (FET) having their gates connected one to the source voltage and one to the drain voltage to provide a linear resistance element. The actual resistance value can be controlled by selecting design parameters and can be extended by using a plurality of such elements in series to provide greater resistances and/or higher voltage capabilities or in parallel to provide greater current capacity. The described resistor is used as a cost and space saving alternate to discrete resistor components and is particularly useful as a part of an integrated circuit in analog type devices.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式