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1. 发明授权

US08589718B2 Performance scaling device, processor having the same, and performance scaling method thereof 有权
标题翻译：性能缩放设备，具有相同性能的处理器及其性能缩放方法
公开(公告)号：US08589718B2
公开(公告)日：2013-11-19
申请号：US12881190
申请日：2010-09-14
申请人： Chi-Hung Lin , Pi-Cheng Hsiao , Tay-Jyi Lin , Gin-Kou Ma
发明人： Chi-Hung Lin , Pi-Cheng Hsiao , Tay-Jyi Lin , Gin-Kou Ma
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a latency prediction unit, and a variable-latency datapath. The adaptive voltage scaling unit generates a plurality of operation voltages and transmits the operation voltages to the variable-latency datapath. The variable-latency datapath operates with different latencies according to the operation voltages and generates an operation latency. The latency prediction unit receives the operation latency and a system latency tolerance and generates a voltage scaling signal for the adaptive voltage scaling unit according to the operation latency and the system latency tolerance. The adaptive voltage scaling unit outputs and scales the operation voltages thereof according to the voltage scaling signal.
摘要翻译：提供了一种性能缩放装置，具有该性能缩放装置的处理器及其性能缩放方法。性能缩放装置包括自适应电压缩放单元，等待时间预测单元和可变延迟数据路径。自适应电压缩放单元产生多个操作电压并将操作电压发送到可变延迟数据路径。可变延迟数据路径根据操作电压运行不同的延迟，并产生运行延迟。延迟预测单元接收操作等待时间和系统等待时间容差，并且根据操作等待时间和系统等待时间容差产生用于自适应电压缩放单元的电压缩放信号。自适应电压调整单元根据电压缩放信号输出并缩放其工作电压。

2. 发明授权

US07406588B2 Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer 有权
标题翻译：动态可重构级流水线数据通路与数据有效信号控制多路复用器
公开(公告)号：US07406588B2
公开(公告)日：2008-07-29
申请号：US11229616
申请日：2005-09-20
申请人： Tay-Jyi Lin , Chein-Wei Jen , Chih-Wei Liu , Po-Han Huang , Wei-Sheng Huang , Chan-Hao Chang
发明人： Tay-Jyi Lin , Chein-Wei Jen , Chih-Wei Liu , Po-Han Huang , Wei-Sheng Huang , Chan-Hao Chang
IPC分类号： G06F9/38
CPC分类号： G06F9/3869
摘要： A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.
摘要翻译：提供了具有动态可重构流水线级的流水线数据路径，具有管线控制器，其生成时钟信号并基于系统时钟和有效数据信号选择信号，以控制流水线电路中的每个寄存器和多路复用器。换句话说，当正在处理有效数据时，激活流水线寄存器来锁存组合逻辑电路的输出; 否则，当接收到无效数据时，寄存器不被激活，并且基准通过多路复用器旁路寄存器。因此，流水线数据路径的流水线级可动态重新配置，有效节省功耗。

3. 发明申请

US20060259748A1 Pipelined datapath with dynamically reconfigurable pipeline stages 有权
标题翻译：具有动态可重构流水线阶段的流水线数据路径
公开(公告)号：US20060259748A1
公开(公告)日：2006-11-16
申请号：US11229616
申请日：2005-09-20
申请人： Tay-Jyi Lin , Chein-Wei Jen , Chih-Wei Liu , Po-Han Huang , Wei-Sheng Huang , Chan-Hao Chang
发明人： Tay-Jyi Lin , Chein-Wei Jen , Chih-Wei Liu , Po-Han Huang , Wei-Sheng Huang , Chan-Hao Chang
IPC分类号： G06F9/44
CPC分类号： G06F9/3869
摘要： A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.
摘要翻译：提供了具有动态可重构流水线级的流水线数据路径，具有管线控制器，其生成时钟信号并基于系统时钟和有效数据信号选择信号，以控制流水线电路中的每个寄存器和多路复用器。换句话说，当正在处理有效数据时，激活流水线寄存器来锁存组合逻辑电路的输出; 否则，当接收到无效数据时，寄存器不被激活，并且基准通过多路复用器旁路寄存器。因此，流水线数据路径的流水线级可动态重新配置，有效节省功耗。

4. 发明申请

US20060212663A1 Inter-cluster communication module using the memory access network 有权
标题翻译：群集间通信模块使用内存接入网
公开(公告)号：US20060212663A1
公开(公告)日：2006-09-21
申请号：US11246115
申请日：2005-10-11
申请人： Tay-Jyi Lin , Pi-Chen Hsiao , Chih-Wei Liu , Chein-Wei Jen , I-Tao Liao , Po-Han Huang
发明人： Tay-Jyi Lin , Pi-Chen Hsiao , Chih-Wei Liu , Chein-Wei Jen , I-Tao Liao , Po-Han Huang
IPC分类号： G06F12/00
CPC分类号： G06F15/173
摘要： An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an identical memory address concurrently, the controller controls the switch device which connects the clusters and the memory banks of the memory subsystem, so that the data item is transmitted from the cluster issuing the store instruction to the cluster issuing the load instruction through the switch device, thereby achieving data exchange between the clusters. Herein, the data item is selectively stored in the memory module depending on the address. Furthermore, the data item is also transmitted between the memory and the clusters over the switch device.
摘要翻译：提供了使用存储器访问网络的集群间通信模块，包括多个集群，存储器子系统，控制器和交换设备。当一些集群发出加载指令并且一些集群同时发出相同存储器地址的存储指令时，控制器控制连接存储器子系统的集群和存储器组的交换设备，从而从集群发送数据项通过交换设备向发布加载指令的集群发出存储指令，由此实现集群之间的数据交换。这里，数据项根据地址被选择性地存储在存储器模块中。此外，数据项也通过交换设备在存储器和簇之间传输。

5. 发明申请

US20110314306A1 PERFORMANCE SCALING DEVICE, PROCESSOR HAVING THE SAME, AND PERFORMANCE SCALING METHOD THEREOF 有权
标题翻译：性能调整装置，具有该功能的处理器及其性能调整方法
公开(公告)号：US20110314306A1
公开(公告)日：2011-12-22
申请号：US12881190
申请日：2010-09-14
申请人： Chi-Hung Lin , Pi-Cheng Hsiao , Tay-Jyi Lin , Gin-Kou Ma
发明人： Chi-Hung Lin , Pi-Cheng Hsiao , Tay-Jyi Lin , Gin-Kou Ma
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a latency prediction unit, and a variable-latency datapath. The adaptive voltage scaling unit generates a plurality of operation voltages and transmits the operation voltages to the variable-latency datapath. The variable-latency datapath operates with different latencies according to the operation voltages and generates an operation latency. The latency prediction unit receives the operation latency and a system latency tolerance and generates a voltage scaling signal for the adaptive voltage scaling unit according to the operation latency and the system latency tolerance. The adaptive voltage scaling unit outputs and scales the operation voltages thereof according to the voltage scaling signal.
摘要翻译：提供了一种性能缩放装置，具有该性能缩放装置的处理器及其性能缩放方法。性能缩放装置包括自适应电压缩放单元，等待时间预测单元和可变延迟数据路径。自适应电压缩放单元产生多个操作电压并将操作电压发送到可变延迟数据路径。可变延迟数据路径根据操作电压运行不同的延迟，并产生运行延迟。延迟预测单元接收操作等待时间和系统等待时间容差，并且根据操作等待时间和系统等待时间容差产生用于自适应电压缩放单元的电压缩放信号。自适应电压调整单元根据电压缩放信号输出并缩放其工作电压。

6. 发明申请

US20110161690A1 VOLTAGE SCALING SYSTEMS 审中-公开
标题翻译：电压调节系统
公开(公告)号：US20110161690A1
公开(公告)日：2011-06-30
申请号：US12972026
申请日：2010-12-17
申请人： Tay-Jyi LIN , Pi-Cheng HSIAO
发明人： Tay-Jyi LIN , Pi-Cheng HSIAO
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3203
摘要： A voltage scaling system is provided and includes a processor, a latency predictor, a controller, and a voltage supplier. The processor performs functions and includes a function unit with variable-latency. The function unit is divided into several power domains. When the processor performs the functions, the function unit generates a latency signal according to a current circuit execution speed. The latency predictor predicts performance of the processor according to the received latency signal to generate a predication signal. The controller compares a value of the predication signal with at least one reference value. The controller generates control signals according to the comparison result. The voltage supplier couples to a first voltage source providing a high voltage and a second voltage source providing a low voltage. The voltage supplier is switched to provide the high or low voltage to the power domains according to the control signals, respectively.
摘要翻译：提供电压缩放系统并且包括处理器，等待时间预测器，控制器和电压供应器。处理器执行功能并且包括具有可变延迟的功能单元。功能单元分为几个电源域。当处理器执行功能时，功能单元根据当前电路执行速度生成等待时间信号。延迟预测器根据接收到的等待时间信号预测处理器的性能以产生预测信号。控制器将预测信号的值与至少一个参考值进行比较。控制器根据比较结果生成控制信号。电压供应器耦合到提供高电压的第一电压源和提供低电压的第二电压源。电压供应器根据控制信号分别切换到电力域的高电压或低电压。

7. 发明授权

US07877741B2 Method and corresponding apparatus for compiling high-level languages into specific processor architectures 有权
标题翻译：用于将高级语言编译成特定处理器架构的方法和相应的装置
公开(公告)号：US07877741B2
公开(公告)日：2011-01-25
申请号：US11246126
申请日：2005-10-11
申请人： Tay-Jyi Lin , Chie-Min Chao , Chih-Wei Liu , Chein-Wei Jen , I-Tao Liao , Po-Han Huang
发明人： Tay-Jyi Lin , Chie-Min Chao , Chih-Wei Liu , Chein-Wei Jen , I-Tao Liao , Po-Han Huang
IPC分类号： G06F9/45 , G06F9/445
CPC分类号： G06F8/447
摘要： A method and corresponding apparatus for compiling high-level languages into specific processor architectures are provided. In this embodiment, the specific processor is encapsulated in a virtual processor interface with simple instruction set architecture, and a compiler translates application programs into corresponding assembly codes. Further, the difficulty of the compiler design is reduced.
摘要翻译：提供了一种用于将高级语言编译成特定处理器架构的方法和相应的装置。在该实施例中，特定处理器被封装在具有简单指令集架构的虚拟处理器接口中，并且编译器将应用程序转换为相应的汇编代码。此外，编译器设计的难度降低。

8. 发明申请

US20050204118A1 Method for inter-cluster communication that employs register permutation 审中-公开
标题翻译：采用寄存器排列的集群间通信方法
公开(公告)号：US20050204118A1
公开(公告)日：2005-09-15
申请号：US10787211
申请日：2004-02-27
申请人： Chein-Wei Jen , Tay-Jyi Lin , Chen-Chia Lee , Chin-Chi Chang , Chih-Wei Liu
发明人： Chein-Wei Jen , Tay-Jyi Lin , Chen-Chia Lee , Chin-Chi Chang , Chih-Wei Liu
IPC分类号： G06F15/00
CPC分类号： G06F9/30032 , G06F9/3012 , G06F9/3828 , G06F9/3891
摘要： The present invention is a method for inter-cluster communication that employs register permutation by dynamically mapping the registers to the functional units. Because only the mapping between registers and functional units is changed and no actual data movement occurs, the present invention greatly diminishes the power consumption. Owing to the inter-cluster communication mechanism, a centralized register file can be replaced with small register sub-blocks, where the silicon area is greatly reduced, and the access time and the power consumption are also diminished.
摘要翻译：本发明是一种群间通信的方法，其通过将寄存器动态映射到功能单元来采用寄存器置换。因为只有寄存器和功能单元之间的映射被改变并且没有发生实际的数据移动，所以本发明大大地降低了功耗。由于集群间通信机制，集中式寄存器文件可以用小的寄存器子块代替，其中硅面积大大减少，访问时间和功耗也减少。

9. 发明申请

US20100050184A1 MULTITASKING PROCESSOR AND TASK SWITCHING METHOD THEREOF 审中-公开
标题翻译：多功能处理器及其任务切换方法
公开(公告)号：US20100050184A1
公开(公告)日：2010-02-25
申请号：US12354753
申请日：2009-01-15
申请人： Tay-Jyi Lin , Pao-Jui Huang , Chih-Wei Liu , Shin-Kai Chen , Bing-Shiun Wang
发明人： Tay-Jyi Lin , Pao-Jui Huang , Chih-Wei Liu , Shin-Kai Chen , Bing-Shiun Wang
IPC分类号： G06F9/46 , G06F13/24 , G06F9/315 , G06F9/30
CPC分类号： G06F9/461 , G06F9/30043 , G06F9/3009 , G06F9/4812 , Y02D10/24
摘要： A multitasking processor and a task switching method thereof are provided. The task switching method includes following steps. A first task is executed by the multitasking processor, wherein the first task contains a plurality of switching-point instructions. An interrupt event occurs. Accordingly, the multitasking processor temporarily stops executing the first task and starts to execute a second task. The multitasking processor executes a handling process of the interrupt event and sets a switching flag. After finishing the handling process of the interrupt event, the multitasking processor does not perform task switching but continues to execute the first task, and the multitasking processor only performs task switching to execute the second task when it reaches a switching-point instruction in the first task.
摘要翻译：提供了一种多任务处理器及其任务切换方法。任务切换方法包括以下步骤。第一任务由多任务处理器执行，其中第一任务包含多个切换点指令。发生中断事件。因此，多任务处理器暂时停止执行第一任务并开始执行第二任务。多任务处理器执行中断事件的处理过程并设置切换标志。在完成中断事件的处理过程之后，多任务处理器不执行任务切换，但是继续执行第一任务，并且多任务处理器仅在第一任务到达切换点指令时执行任务切换以执行第二任务任务。

10. 发明授权

US07404048B2 Inter-cluster communication module using the memory access network 有权
标题翻译：群集间通信模块使用内存接入网
公开(公告)号：US07404048B2
公开(公告)日：2008-07-22
申请号：US11246115
申请日：2005-10-11
申请人： Tay-Jyi Lin , Pi-Chen Hsiao , Chih-Wei Liu , Chein-Wei Jen , I-Tao Liao , Po-Han Huang
发明人： Tay-Jyi Lin , Pi-Chen Hsiao , Chih-Wei Liu , Chein-Wei Jen , I-Tao Liao , Po-Han Huang
IPC分类号： G06F12/00
CPC分类号： G06F15/173
摘要： An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an identical memory address concurrently, the controller controls the switch device which connects the clusters and the memory banks of the memory subsystem, so that the data item is transmitted from the cluster issuing the store instruction to the cluster issuing the load instruction through the switch device, thereby achieving data exchange between the clusters. Herein, the data item is selectively stored in the memory module depending on the address. Furthermore, the data item is also transmitted between the memory and the clusters over the switch device.
摘要翻译：提供了使用存储器访问网络的集群间通信模块，包括多个集群，存储器子系统，控制器和交换设备。当一些集群发出加载指令并且一些集群同时发出相同存储器地址的存储指令时，控制器控制连接存储器子系统的集群和存储器组的交换设备，从而从集群发送数据项通过交换设备向发布加载指令的集群发出存储指令，从而实现集群之间的数据交换。这里，数据项根据地址被选择性地存储在存储器模块中。此外，数据项也通过交换设备在存储器和簇之间传输。

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