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1. 发明授权

US08589718B2 Performance scaling device, processor having the same, and performance scaling method thereof 有权
标题翻译：性能缩放设备，具有相同性能的处理器及其性能缩放方法
公开(公告)号：US08589718B2
公开(公告)日：2013-11-19
申请号：US12881190
申请日：2010-09-14
申请人： Chi-Hung Lin , Pi-Cheng Hsiao , Tay-Jyi Lin , Gin-Kou Ma
发明人： Chi-Hung Lin , Pi-Cheng Hsiao , Tay-Jyi Lin , Gin-Kou Ma
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a latency prediction unit, and a variable-latency datapath. The adaptive voltage scaling unit generates a plurality of operation voltages and transmits the operation voltages to the variable-latency datapath. The variable-latency datapath operates with different latencies according to the operation voltages and generates an operation latency. The latency prediction unit receives the operation latency and a system latency tolerance and generates a voltage scaling signal for the adaptive voltage scaling unit according to the operation latency and the system latency tolerance. The adaptive voltage scaling unit outputs and scales the operation voltages thereof according to the voltage scaling signal.
摘要翻译：提供了一种性能缩放装置，具有该性能缩放装置的处理器及其性能缩放方法。性能缩放装置包括自适应电压缩放单元，等待时间预测单元和可变延迟数据路径。自适应电压缩放单元产生多个操作电压并将操作电压发送到可变延迟数据路径。可变延迟数据路径根据操作电压运行不同的延迟，并产生运行延迟。延迟预测单元接收操作等待时间和系统等待时间容差，并且根据操作等待时间和系统等待时间容差产生用于自适应电压缩放单元的电压缩放信号。自适应电压调整单元根据电压缩放信号输出并缩放其工作电压。

2. 发明申请

US20110314306A1 PERFORMANCE SCALING DEVICE, PROCESSOR HAVING THE SAME, AND PERFORMANCE SCALING METHOD THEREOF 有权
标题翻译：性能调整装置，具有该功能的处理器及其性能调整方法
公开(公告)号：US20110314306A1
公开(公告)日：2011-12-22
申请号：US12881190
申请日：2010-09-14
申请人： Chi-Hung Lin , Pi-Cheng Hsiao , Tay-Jyi Lin , Gin-Kou Ma
发明人： Chi-Hung Lin , Pi-Cheng Hsiao , Tay-Jyi Lin , Gin-Kou Ma
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a latency prediction unit, and a variable-latency datapath. The adaptive voltage scaling unit generates a plurality of operation voltages and transmits the operation voltages to the variable-latency datapath. The variable-latency datapath operates with different latencies according to the operation voltages and generates an operation latency. The latency prediction unit receives the operation latency and a system latency tolerance and generates a voltage scaling signal for the adaptive voltage scaling unit according to the operation latency and the system latency tolerance. The adaptive voltage scaling unit outputs and scales the operation voltages thereof according to the voltage scaling signal.
摘要翻译：提供了一种性能缩放装置，具有该性能缩放装置的处理器及其性能缩放方法。性能缩放装置包括自适应电压缩放单元，等待时间预测单元和可变延迟数据路径。自适应电压缩放单元产生多个操作电压并将操作电压发送到可变延迟数据路径。可变延迟数据路径根据操作电压运行不同的延迟，并产生运行延迟。延迟预测单元接收操作等待时间和系统等待时间容差，并且根据操作等待时间和系统等待时间容差产生用于自适应电压缩放单元的电压缩放信号。自适应电压调整单元根据电压缩放信号输出并缩放其工作电压。

3. 发明申请

US20080118003A1 Enhanced Wireless Communication System and Method Thereof 审中-公开
标题翻译：增强型无线通信系统及其方法
公开(公告)号：US20080118003A1
公开(公告)日：2008-05-22
申请号：US12023341
申请日：2008-01-31
申请人： Wen-Chung Liu , Gin-Kou Ma
发明人： Wen-Chung Liu , Gin-Kou Ma
IPC分类号： H04L27/20
CPC分类号： H04L27/186 , H04L1/0618
摘要： A communication system comprising a channel encoder to generate a binary bit stream, a mapping unit coupled to the channel encoder, the mapping unit configured to receive the binary bit stream from the channel encoder and to map every “n” consecutive bits of the binary bit stream into a symbol in accordance with a mapping table, wherein the symbol has a symbol value related to a modulation mode, “n” being a positive integer, and a number of “m” modulation units coupled to the mapping unit, “m” being a positive integer, the modulation units configured to receive a set of “m” symbols from the mapping unit and modulate the set of “m” symbols based on the modulation mode, wherein a combined value of the symbol values of the set of “m” symbols from the mapping unit is distinguishable from another combined value of the symbol values of another set of “m” symbols from the mapping unit, and wherein a combined value of the symbol values of a set of “m” symbols from the mapping unit corresponds to a distinguishable bit value of the “n” consecutive bits in the binary bit stream.
摘要翻译：一种通信系统，包括用于产生二进制比特流的信道编码器，耦合到信道编码器的映射单元，该映射单元被配置为从信道编码器接收二进制比特流并映射二进制位的每个“n”个连续比特根据映射表流入符号，其中符号具有与调制模式相关的符号值，“n”为正整数，以及耦合到映射单元的“m”个调制单元的数量，“m” 作为正整数，所述调制单元被配置为从所述映射单元接收一组“m”个符号，并且基于所述调制模式来调制所述一组“m”个符号，其中，所述“ 来自映射单元的“m”符号与来自映射单元的另一组“m”符号的符号值的另一组合值是可区分的，并且其中来自映射的一组“m”符号的符号值的组合值单位对应到二进制比特流中的“n”个连续比特的可区分比特值。

4. 发明授权

US06279040B1 Scalable architecture for media-on demand servers 有权
标题翻译：适用于媒体点播服务器的可扩展架构
公开(公告)号：US06279040B1
公开(公告)日：2001-08-21
申请号：US09300826
申请日：1999-04-27
申请人： Gin-Kou Ma , Chiung-Shien Wu , Muh-Rong Yang
发明人： Gin-Kou Ma , Chiung-Shien Wu , Muh-Rong Yang
IPC分类号： G06F1300
CPC分类号： H04L29/06 , H04J3/0632 , H04J3/247 , H04L67/42 , H04L2012/5651 , H04L2012/5672 , H04L2012/5679 , H04Q11/0478
摘要： A scalable server architecture for use in implementing scaled media servers capable of simultaneous real-time data stream retrieval for large numbers of subscribers. A scalable server includes a plurality of stream pumping engines each accessing a particular storage device of a storage subsystem, and a server processor which receives retrieval requests from subscribers and directs the stream pumping engines to retrieve the requested data streams. Each of the stream pumping engines may include a storage controller coupled to its corresponding storage device for directing retrieval of the requested stream therefrom, a network controller for supplying the retrieved stream to a client network, and a processor for directing the operation of the storage and network controllers. Each of the stream pumping engines may also include a shared memory accessible by the corresponding stream pumping engine processor and the server processor. The shared memory facilitates communication with other stream pumping engines via the server processor and server system bus. A scaled media server may be implemented by cross-connecting several scalable servers with a plurality of stream multiplexers. Each of the stream multiplexers can include a separate packet input unit for processing the packets of each media stream such that two distinct levels of transmission priority are provided and quality of server restrictions are satisfied for all streams.
摘要翻译：一种可扩展的服务器体系结构，用于实现能够为大量用户同时进行实时数据流检索的缩放媒体服务器。可扩展服务器包括每个访问存储子系统的特定存储设备的多个流泵送引擎，以及服务器处理器，其接收来自订户的检索请求并指示流泵送引擎检索所请求的数据流。每个流泵送引擎可以包括耦合到其相应的存储设备的存储控制器，用于指示从其中检索所请求的流，网络控制器，用于将检索到的流提供给客户端网络;以及处理器，用于指导存储器的操作，以及网络控制器每个流泵送引擎还可以包括由相应的流泵送引擎处理器和服务器处理器可访问的共享存储器。共享内存便于通过服务器处理器和服务器系统总线与其他流泵送引擎进行通信。可以通过将多个可扩展服务器与多个流多路复用器交叉连接来实现缩放的媒体服务器。每个流多路复用器可以包括单独的分组输入单元，用于处理每个媒体流的分组，使得提供两个不同级别的传输优先级，并且对于所有流来满足服务器限制的质量。

5. 发明申请

US20080208944A1 DIGITAL SIGNAL PROCESSOR STRUCTURE FOR PERFORMING LENGTH-SCALABLE FAST FOURIER TRANSFORMATION 审中-公开
标题翻译：用于执行长度可扩展的快速傅立叶变换的数字信号处理器结构
公开(公告)号：US20080208944A1
公开(公告)日：2008-08-28
申请号：US12115820
申请日：2008-05-06
申请人： Cheng-Han Sung , Chein-Wei Jen , Chih-Wei Liu , Hung-Chi Lai , Gin-Kou Ma
发明人： Cheng-Han Sung , Chein-Wei Jen , Chih-Wei Liu , Hung-Chi Lai , Gin-Kou Ma
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： A digital signal processor structure by performing length-scalable Fast Fourier Transformation (FFT) discloses a single processor element (single PE), and a simple and effective address generator are used to achieve length-scalable, high performance, and low power consumption in split-radix-2/4 FFT or IFFT module. In order to meet different communication standards, the digital signal processor structure has run-time configuration to perform for different length requirements. Moreover, its execution time can fit the standards of Fast Fourier Transformation (FFT) or Inverse Fast Fourier Transformation (IFFT).
摘要翻译：通过执行长度可缩放的快速傅里叶变换（FFT）的数字信号处理器结构公开了单个处理器元件（单个PE），并且使用简单而有效的地址发生器来实现长度可分级，高性能和低功耗的拆分 -radix-2/4 FFT或IFFT模块。为了满足不同的通信标准，数字信号处理器结构具有执行不同长度要求的运行时配置。此外，其执行时间可以适应快速傅里叶变换（FFT）或快速傅里叶逆变换（IFFT）的标准。

6. 发明申请

US20060165155A1 System and method for ultra-wideband (UWB) communication transceiver 有权
公开(公告)号：US20060165155A1
公开(公告)日：2006-07-27
申请号：US11212700
申请日：2005-08-29
申请人： Wen-Chung Liu , Gin-Kou Ma
发明人： Wen-Chung Liu , Gin-Kou Ma
IPC分类号： H04B1/69 , H04L1/02
CPC分类号： H04B1/71632 , H04B1/71635 , H04L1/0068
摘要： An ultra-wideband (UWB) transceiver for use in UWB communication includes a voltage-controlled oscillator (VCO) configured to periodically and sequentially generate a series of base frequencies based on a predetermined sequence and a waveform generator to generate carrier waves based on the generated base frequencies.

7. 发明授权

US5940389A Enhanced partially self-routing algorithm for controller Benes networks 失效
标题翻译：用于控制器Benes网络的增强的部分自路由算法
公开(公告)号：US5940389A
公开(公告)日：1999-08-17
申请号：US854395
申请日：1997-05-12
申请人： Muh-rong Yang , Gin-Kou Ma
发明人： Muh-rong Yang , Gin-Kou Ma
IPC分类号： H04J3/14
CPC分类号： H04L49/1507 , H04L49/254
摘要： A system and method are provided for assigning routing tag bits for routing signals through a Benes network comprising an input stage and an output stage. The input and output stages each comprise a column of 2.times.2 .beta. elements which route an inputted signal to an upper output if the control sequence bit is 0 and to a lower output if the control sequence bit is 1. Each signal inputted to the Benes network is associated with control sequence. For a particular Benes, in a particular control stage of the Benes network, a 0 is assigned to a control sequence bit associated with a signal q.sub.0 received at an upper input of a topmost input stage .beta. element. A 1 is assigned to a control sequence bit associated with a signal q.sub.k received at the same output stage p element as the signal q.sub.0. A 1 is assigned to a control sequence bit associated with a signal q.sub.1 received at a lower input of the topmost input stage .beta. element. A 0 to is assigned to a control sequence bit associated with a signal q.sub.k ' received at the same output stage .beta. element as the signal q.sub.1. For at least one signal q.sub.p for which no control sequence bit is yet assigned, either a 0 or a 1 is assigned to the control sequence bit associated with the signal q.sub.p. The complement of the chosen control sequence bit is assigned to a control sequence bit associated with a signal q.sub.k " received at the same output stage .beta. element as the signal q.sub.p.
摘要翻译：提供了一种系统和方法，用于通过包括输入级和输出级的Benes网络为路由信号分配路由标签位。如果控制序列位为0，则输入和输出级各自包括2×2β元件的列，其将输入的信号路由到上输出，并且如果控制序列位为1，则将其输入到较低的输出。输入到Benes网络的每个信号是与控制序列相关。对于特定的Benes，在Benes网络的特定控制级中，将0分配给与在最上面的输入级β元件的上部输入处接收的信号q0相关联的控制序列位。 A 1被分配给与在与信号q0相同的输出级p元件处接收的信号qk相关联的控制序列位。 A 1被分配给与在最上面的输入级β元件的较低输入处接收的信号q1相关联的控制序列位。 A 0被分配给与在与信号q1相同的输出级β元件处接收的信号qk'相关联的控制序列位。对于尚未分配控制序列位的至少一个信号qp，将0或1分配给与信号qp相关联的控制序列位。所选择的控制序列位的补码被分配给与在与信号qp相同的输出级β元件处接收的信号qk“相关联的控制序列位。

8. 发明授权

US5926649A Media server for storage and retrieval of voluminous multimedia data 失效
标题翻译：用于存储和检索大量多媒体数据的媒体服务器
公开(公告)号：US5926649A
公开(公告)日：1999-07-20
申请号：US736215
申请日：1996-10-23
申请人： Gin-Kou Ma , Chiung-Shien Wu , Muh-Rong Yang
发明人： Gin-Kou Ma , Chiung-Shien Wu , Muh-Rong Yang
IPC分类号： G06F9/48 , G06F13/37
CPC分类号： G06F9/4887
摘要： A method and apparatus for storage and retrieval of multiple data streams in a multimedia distribution system. A given data stream is separated into a plurality of portions, and the portions are stored in a multi-disk storage system with Y disks each having X zones such that the ith portion of the given stream is stored in zone (i mod X) of disk (i mod Y). The number X of zones per disk and the number Y of disks are selected as relatively prime numbers. The stored data are retrieved using Y independent retrieval schedulers which are circulated among the Y disks over a number of scheduling intervals. Each retrieval scheduler processes multiple requests separated into X groups, with the requests of each group accessing the same disk zone during a given scheduling interval. The retrieval schedulers are also configured such that the retrieval requests of a given retrieval scheduler access the same disk during a given scheduling interval. The data stream placement technique in conjunction with the retrieval schedulers provide sequential-like parallel retrieval suitable for supporting real-time multimedia data distribution for large numbers of clients.
摘要翻译：一种用于在多媒体分发系统中存储和检索多个数据流的方法和装置。给定的数据流被分成多个部分，并且这些部分被存储在多盘存储系统中，每个Y盘具有X个区域，使得给定流的第i个部分被存储在磁盘（i mod Y）。选择每个磁盘区域的数量X和磁盘的数量Y作为相对素数。使用Y个独立的检索调度器检索存储的数据，这些调度器在多个调度间隔中在Y个盘之间循环。每个检索调度程序处理分离成X组的多个请求，每个组的请求在给定的调度间隔期间访问相同的磁盘区。检索调度器还被配置为使得给定检索调度程序的检索请求在给定调度间隔期间访问相同的盘。数据流放置技术与检索调度器一起提供了适合于支持大量客户端的实时多媒体数据分发的顺序式并行检索。

9. 发明授权

US08254489B2 Transmission method and multiple input multiple output wireless communication system using the same 有权
标题翻译：传输方式和多输入多输出无线通信系统使用相同
公开(公告)号：US08254489B2
公开(公告)日：2012-08-28
申请号：US12406948
申请日：2009-03-18
申请人： Wen-Chung Liu , Gin-Kou Ma , Muh-Rong Yang
发明人： Wen-Chung Liu , Gin-Kou Ma , Muh-Rong Yang
IPC分类号： H04B7/02 , H04K1/10 , H04L27/28 , H03C5/00 , H03K7/02
CPC分类号： H04B7/0426
摘要： A transmission method executed in a multiple input multiple output wireless communication system may include the following steps: receiving a transmitting bit sequence; providing an X level pulse amplitude modulation (X-PAM) signal set, wherein distances between any two adjacent signal points in the X-PAM are the same; generating M signal sets according to the X-PAM signal set, wherein the ith signal set is formed by multiplying the X-PAM signal set with a parameter (1/X)(i−1), wherein i is an integer from 1 to M, and generating a X-PAM signal set joint coding/decoding table according a superposition result of the M signal sets; generating M transmitting bit sub-sequences according to the transmitting bit sequence; generating M transmitting signals according to the M transmitting bit sub-sequences and the X-PAM signal set joint coding/decoding table; transmitting the M transmitting signals to a wireless transmission channel via M transmitting antennae.
摘要翻译：在多输入多输出无线通信系统中执行的发送方法可以包括以下步骤：接收发送比特序列; 提供X级脉冲幅度调制（X-PAM）信号组，其中X-PAM中任意两个相邻信号点之间的距离相同; 根据X-PAM信号组生成M个信号组，其中第i个信号组是通过将X-PAM信号集合与参数（1 / X）（i-1）相乘形成的，其中i是从1到 M，并根据M个信号集合的叠加结果生成X-PAM信号集合编码/解码表; 根据发送比特序列产生M个发送比特子序列; 根据M个发送比特子序列和X-PAM信号集合编码/解码表生成M个发送信号; 通过M个发送天线将M个发送信号发送到无线传输信道。

10. 发明授权

US6014545A Growable architecture for high-speed two-way data services over CATV networks 失效
标题翻译：通过CATV网络实现高速双向数据业务的可扩展架构
公开(公告)号：US6014545A
公开(公告)日：2000-01-11
申请号：US827175
申请日：1997-03-27
申请人： Chiung-Shien Wu , Gin-Kou Ma
发明人： Chiung-Shien Wu , Gin-Kou Ma
IPC分类号： H04H60/96 , H04L12/46 , H04N7/10 , H04N7/173 , H04N21/61
CPC分类号： H04N7/17309 , H04H60/96 , H04L12/46 , H04N21/6118 , H04N21/6168 , H04N7/10
摘要： A cable network is provided with at least one bridge that is connected to a first cable segment of the cable network. The bridge receives from a shared communication medium a first carrier signal, having a first carrier frequency that is allocated for intra cable segment packet communication, containing packets modulated thereon. The bridge demodulates selected packets originating in the first cable segment from the first carrier signal. The bridge modulates each of the demodulated packets, that are destined outside of the first cable segment, onto a second carrier signal having a second carrier frequency. The bridge then transmits the second carrier signal on an upstream link of the common shared medium.
摘要翻译：电缆网络设置有至少一个连接到电缆网络的第一电缆段的桥。桥接器从共享通信介质接收第一载波信号，该第一载波信号具有被分配用于内部电缆段分组通信的第一载波频率，包含在其上调制的分组。桥从第一载波信号解调来自第一电缆段的所选分组。桥将调制在第一电缆段之外的每个解调的分组调制到具有第二载波频率的第二载波信号上。桥接器然后在公共共享介质的上游链路上发送第二载波信号。

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