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1. 发明申请

US20160284119A1 Hardware Based Free Lists for Multi-Rate Shader 审中-公开
标题翻译：基于硬件的多速率着色器的免费列表
公开(公告)号：US20160284119A1
公开(公告)日：2016-09-29
申请号：US14666463
申请日：2015-03-24
申请人： Prasoonkumar Surti , Thomas A. Piazza
发明人： Prasoonkumar Surti , Thomas A. Piazza
IPC分类号： G06T15/80 , G06T17/10 , G06T1/60
CPC分类号： G06T1/60 , G06T15/005 , G06T15/80
摘要： A group of buffers are connected via pointers as free-lists implemented in hardware, such that shader information and output processing information can be efficiently accessed by a multi-rate shader. A free-list storage picks the first available entry. The first free entry that gets allocated then becomes a pointer to another entry.
摘要翻译：一组缓冲器通过指针作为在硬件中实现的自由列表连接，使得可以通过多速率着色器有效地访问着色器信息和输出处理信息。免费列表存储选择第一个可用条目。获得分配的第一个空闲条目将成为另一条目的指针。

2. 发明授权

US09235926B2 Techniques for improving MSAA rendering efficiency 有权
标题翻译：提高MSAA渲染效率的技术
公开(公告)号：US09235926B2
公开(公告)日：2016-01-12
申请号：US13726362
申请日：2012-12-24
申请人： Prasoonkumar Surti , Thomas A. Piazza
发明人： Prasoonkumar Surti , Thomas A. Piazza
IPC分类号： G06T15/00 , G06T15/50 , G06T11/40
CPC分类号： G06T15/503 , G06T11/40 , G06T15/005 , G06T2200/12 , G06T2210/08
摘要： Various embodiments are generally directed to techniques for causing the storage of a color data value of a clear color to be deferred as rendered color data values are stored for samples. A device comprises a processor circuit and a storage to store instructions that cause the processor circuit to render a pixel from multiple samples taken of a three-dimensional model of an object, the pixel corresponding to a pixel sample data which comprises multiple color storage locations that are each identified by a numeric identifier, and which comprises multiple sample color indices that each correspond to a sample to point to at least one color storage location; and allocate color storage locations in an order selected to define a subset of possible combinations of binary index values among all of the sample color indices as invalid combinations. Other embodiments are described and claimed.
摘要翻译：各种实施例通常涉及用于在为样本存储所渲染的颜色数据值时使得清除颜色的颜色数据值的存储被延迟的技术。一种设备包括处理器电路和存储器，用于存储使得处理器电路从取自对象的三维模型的多个样本呈现像素的指令，所述像素对应于包括多个颜色存储位置的像素样本数据，每个由数字标识符标识，并且其包括多个样本颜色索引，每个样本颜色索引对应于样本以指向至少一个颜色存储位置; 并且以所选择的顺序分配颜色存储位置，以将所有样本颜色索引中的二进制索引值的可能组合的子集定义为无效组合。描述和要求保护其他实施例。

3. 发明申请

US20140347385A1 LOSSY COLOR MERGE FOR MULTI-SAMPLING ANTI-ALIASING COMPRESSION 有权
标题翻译：用于多采样抗锯齿压缩的丢失颜色合成
公开(公告)号：US20140347385A1
公开(公告)日：2014-11-27
申请号：US13901117
申请日：2013-05-23
申请人： Tomas G. Akenine-Moller , Thomas A. Piazza , Prasoonkumar Surti
发明人： Tomas G. Akenine-Moller , Thomas A. Piazza , Prasoonkumar Surti
IPC分类号： G06T5/00
CPC分类号： G06T5/002 , G06T9/00 , G06T11/40 , G06T15/503
摘要： Techniques related to graphics rendering including lossy color merge for multi-sampling anti-aliasing compression are discussed.
摘要翻译：讨论了与图形渲染相关的技术，包括用于多采样抗锯齿压缩的有损颜色合并。

4. 发明申请

US20140176541A1 TECHNIQUES FOR IMPROVING MSAA RENDERING EFFICIENCY 有权
标题翻译：改进MSAA渲染效率的技术
公开(公告)号：US20140176541A1
公开(公告)日：2014-06-26
申请号：US13726362
申请日：2012-12-24
申请人： PRASOONKUMAR SURTI , THOMAS A. PIAZZA
发明人： PRASOONKUMAR SURTI , THOMAS A. PIAZZA
IPC分类号： G06T15/50
CPC分类号： G06T15/503 , G06T11/40 , G06T15/005 , G06T2200/12 , G06T2210/08
摘要： Various embodiments are generally directed to techniques for causing the storage of a color data value of a clear color to be deferred as rendered color data values are stored for samples. A device comprises a processor circuit and a storage to store instructions that cause the processor circuit to render a pixel from multiple samples taken of a three-dimensional model of an object, the pixel corresponding to a pixel sample data which comprises multiple color storage locations that are each identified by a numeric identifier, and which comprises multiple sample color indices that each correspond to a sample to point to at least one color storage location; and allocate color storage locations in an order selected to define a subset of possible combinations of binary index values among all of the sample color indices as invalid combinations. Other embodiments are described and claimed.
摘要翻译：各种实施例通常涉及用于在为样本存储所渲染的颜色数据值时使得清除颜色的颜色数据值的存储被延迟的技术。一种设备包括处理器电路和存储器，用于存储使得处理器电路从取自对象的三维模型的多个样本呈现像素的指令，所述像素对应于包括多个颜色存储位置的像素样本数据，每个由数字标识符标识，并且其包括多个样本颜色索引，每个样本颜色索引对应于样本以指向至少一个颜色存储位置; 并且以所选择的顺序分配颜色存储位置，以将所有样本颜色索引中的二进制索引值的可能组合的子集定义为无效组合。描述和要求保护其他实施例。

5. 发明授权

US08601177B2 Dynamic allocation of a buffer across multiple clients in a threaded processor 有权
标题翻译：在线程处理器中跨多个客户机动态分配缓冲区
公开(公告)号：US08601177B2
公开(公告)日：2013-12-03
申请号：US13534259
申请日：2012-06-27
申请人： Thomas A. Piazza
发明人： Thomas A. Piazza
IPC分类号： G06F12/00 , G06F9/312 , G06F9/22
CPC分类号： G06F9/5016 , G06F12/023
摘要： A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data.
摘要翻译：一种方法可以包括在第一流水线中的第一组函数中分配存储器中的地址范围。第一管道中的第一组功能可以使用地址范围对数据进行操作。可以在第二流水线中的第二组功能中重新分配存储器中的不同范围的地址，而不等待第一组功能被刷新数据。

6. 发明申请

US20130207987A1 TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS 审中-公开
公开(公告)号：US20130207987A1
公开(公告)日：2013-08-15
申请号：US13844214
申请日：2013-03-15
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
IPC分类号： G06T1/60
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

7. 发明授权

US08448179B2 Processing architecture having passive threads and active semaphores 有权
标题翻译：具有被动线程和主动信号量的处理架构
公开(公告)号：US08448179B2
公开(公告)日：2013-05-21
申请号：US13012068
申请日：2011-01-24
申请人： Hong Jiang , Thomas A. Piazza
发明人： Hong Jiang , Thomas A. Piazza
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087 , G06F9/3009 , G06F9/3851 , G06F9/526
摘要： Multiple parallel passive threads of instructions coordinate access to shared resources using “active” semaphores. The semaphores are referred to as active because the semaphores send messages to execution and/or control circuitry to cause the state of a thread to change. A thread can be placed in an inactive state by a thread scheduler in response to an unresolved dependency, which can be indicated by a semaphore. A thread state variable corresponding to the dependency is used to indicate that the thread is in inactive mode. When the dependency is resolved a message is passed to control circuitry causing the dependency variable to be cleared. In response to the cleared dependency variable the thread is placed in an active state. Execution can proceed on the threads in the active state.
摘要翻译：指令的多个并行被动线程使用“活动”信号量协调对共享资源的访问。信号量被称为活动的，因为信号量向执行和/或控制电路发送消息以使得线程的状态改变。线程调度程序可以响应未解决的依赖关系将线程置于无效状态，这可以由信号量指示。与依赖关系对应的线程状态变量用于指示线程处于非活动模式。当依赖关系被解析时，消息被传递给控制电路，导致依赖变量被清除。响应于清除的依赖变量，线程处于活动状态。处于活动状态的线程可执行。

8. 发明授权

US08271986B2 Visual and graphical data processing using a multi-threaded architecture 有权
标题翻译：使用多线程架构的视觉和图形数据处理
公开(公告)号：US08271986B2
公开(公告)日：2012-09-18
申请号：US10750589
申请日：2003-12-31
申请人： Hong Jiang , Thomas A. Piazza
发明人： Hong Jiang , Thomas A. Piazza
IPC分类号： G06F9/46
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30087 , G06F9/52
摘要： Active and/or proactive semaphore mechanisms and thread synchronization techniques can be applied to various visual and graphical processing techniques.
摘要翻译：主动和/或主动信号量机制和线程同步技术可以应用于各种视觉和图形处理技术。

9. 发明授权

US08225012B2 Dynamic allocation of a buffer across multiple clients in a threaded processor 有权
标题翻译：在线程处理器中跨多个客户机动态分配缓冲区
公开(公告)号：US08225012B2
公开(公告)日：2012-07-17
申请号：US12553216
申请日：2009-09-03
申请人： Thomas A. Piazza
发明人： Thomas A. Piazza
IPC分类号： G06F12/00 , G06F9/312 , G06F9/22
CPC分类号： G06F9/5016 , G06F12/023
摘要： A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data.
摘要翻译：一种方法可以包括在第一流水线中的第一组函数中分配存储器中的地址范围。第一管道中的第一组功能可以使用地址范围对数据进行操作。可以在第二流水线中的第二组功能中重新分配存储器中的不同范围的地址，而不等待第一组功能被刷新数据。

10. 发明授权

US07975272B2 Thread queuing method and apparatus 有权
标题翻译：线程排队方法和设备
公开(公告)号：US07975272B2
公开(公告)日：2011-07-05
申请号：US11647608
申请日：2006-12-30
申请人： Hong Jiang , Thomas A. Piazza , Brian D. Rauchfuss , Sreedevi Chalasani , Steven J. Spangler
发明人： Hong Jiang , Thomas A. Piazza , Brian D. Rauchfuss , Sreedevi Chalasani , Steven J. Spangler
IPC分类号： G06F9/46 , G06F15/00
CPC分类号： G06F9/546
摘要： In some embodiments, a method includes receiving a request to generate a thread and supplying a request to a queue in response at least to the received request. The method may further include fetching a plurality of instructions in response at least in part to the request supplied to the queue and executing at least one of the plurality of instructions. In some embodiments, an apparatus includes a storage medium having stored therein instructions that when executed by a machine result in the method. In some embodiments, an apparatus includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request. In some embodiments, a system includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request, and a memory unit to store at least one instruction for the thread.
摘要翻译：在一些实施例中，一种方法包括接收生成线程的请求并至少响应于所接收的请求向队列提供请求。该方法还可以包括至少部分地响应于提供给队列的请求并且执行多个指令中的至少一个指令来获取多个指令。在一些实施例中，装置包括存储介质，其中存储有当机器执行时产生该方法的指令。在一些实施例中，一种装置包括用于接收生成线程的请求并至少对接收到的请求作出响应来排队请求生成线程的电路。在一些实施例中，系统包括电路，用于接收生成线程的请求，并至少响应于所接收到的请求来对请求进行排队以生成线程;以及存储器单元，用于存储线程的至少一条指令。

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