专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09026769B1 Detecting and reissuing of loop instructions in reorder structure 有权
标题翻译：在重新排序结构中检测和重新发行循环指令
公开(公告)号：US09026769B1
公开(公告)日：2015-05-05
申请号：US13357567
申请日：2012-01-24
申请人： Sujat Jamil , R. Frank O'Bleness , Joseph Delgross , Tom Hameenanttila
发明人： Sujat Jamil , R. Frank O'Bleness , Joseph Delgross , Tom Hameenanttila
IPC分类号： G06F9/38 , G06F9/32
CPC分类号： G06F9/3855 , G06F9/325 , G06F9/381 , G06F9/3836
摘要： A processor for processing loop instructions can include an instruction reorder structure and a loop processing controller. The instruction reorder structure is configured to store decoded instructions according to program order and issue the decoded instructions for execution out of program order. The loop processing controller is configured to detect a loop in the decoded instructions stored in the instruction reorder structure and cause the instruction reorder structure to reissue the decoded instructions that form the loop for re-execution.
摘要翻译：用于处理循环指令的处理器可以包括指令重排序结构和循环处理控制器。指令重排结构被配置为根据程序顺序存储解码指令，并发出解码指令以执行程序顺序。循环处理控制器被配置为检测存储在指令重排序结构中的解码指令中的循环，并使指令重排序结构重新发出构成循环的解码指令以便重新执行。

2. 发明授权

US08943273B1 Method and apparatus for improving cache efficiency 有权
标题翻译：提高缓存效率的方法和装置
公开(公告)号：US08943273B1
公开(公告)日：2015-01-27
申请号：US12541277
申请日：2009-08-14
申请人： Sujat Jamil , R. Frank O'Bleness , Russell Robideau , Tom Hameenanttila , Joseph Delgross , David Miner
发明人： Sujat Jamil , R. Frank O'Bleness , Russell Robideau , Tom Hameenanttila , Joseph Delgross , David Miner
IPC分类号： G06F9/38
CPC分类号： G06F12/0875 , G06F9/30043 , G06F9/3826 , G06F9/3842 , G06F9/3859 , G06F12/0804 , G06F2212/452
摘要： Aspects of the disclosure provide methods for cache efficiency. A method for cache efficiency can include storing data in a buffer entry in association with a cache array in response to a first store instruction that hits the cache array before the first store instruction is committed. Further, when a dependent load instruction is subsequent to the first store instruction, the method can include providing the data from the buffer entry in response to the first dependent load instruction. When a second store instruction overlaps an address of the first store instruction, the method can include coalescing data of the second store instruction in the buffer entry before the second store instruction is committed. When the second store instruction is followed by a second dependent load instruction, the method can include providing the coalesced data from the buffer entry in response to the second dependent load instruction.
摘要翻译：本公开的方面提供了缓存效率的方法。一种用于高速缓存效率的方法可以包括：响应于第一个存储指令在第一个存储指令被提交之前触发高速缓冲存储器阵列，将数据与高速缓冲存储器阵列相关联地存储在缓冲器条目中。此外，当依赖加载指令在第一存储指令之后时，该方法可以包括响应于第一依赖加载指令从缓冲器条目提供数据。当第二存储指令与第一存储指令的地址重叠时，该方法可以包括在提交第二存储指令之前将缓冲器条目中的第二存储指令的数据合并。当第二存储指令后跟第二相关加载指令时，该方法可以包括响应于第二依赖加载指令从缓冲器条目提供合并的数据。

3. 发明授权

US08990505B1 Cache memory bank selection 有权
标题翻译：高速缓存存储库选择
公开(公告)号：US08990505B1
公开(公告)日：2015-03-24
申请号：US12235251
申请日：2008-09-22
申请人： Sujat Jamil , R. Frank O'Bleness , David E. Miner , Joseph Delgross , Tom Hameenanttila
发明人： Sujat Jamil , R. Frank O'Bleness , David E. Miner , Joseph Delgross , Tom Hameenanttila
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F12/0864 , G06F12/0871 , G06F2212/1016 , G06F2212/1028 , G06F2212/502 , G06F2212/6082 , Y02D10/13
摘要： Devices, systems, methods, and other embodiments associated with a cache memory are described. In one embodiment, a cache tag array includes tag banks. The cache memory further includes a bank selector configured to receive an address and to apply a hash function that maps the address to one of the tag banks.
摘要翻译：描述了与高速缓冲存储器相关联的设备，系统，方法和其他实施例。在一个实施例中，高速缓存标签阵列包括标签库。高速缓冲存储器还包括配置成接收地址并且应用将地址映射到标签组之一的散列函数的存储体选择器。

4. 发明授权

US08631206B1 Way-selecting translation lookaside buffer 失效
标题翻译：方式选择翻译后备缓冲区
公开(公告)号：US08631206B1
公开(公告)日：2014-01-14
申请号：US12194841
申请日：2008-08-20
申请人： R. Frank O'Bleness , Sujat Jamil , David E. Miner , Joseph Delgross , Tom Hameenanttila
发明人： R. Frank O'Bleness , Sujat Jamil , David E. Miner , Joseph Delgross , Tom Hameenanttila
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/1054 , G06F12/0864 , Y02D10/13
摘要： Set-associative caches having corresponding methods and computer programs comprise: a data cache to provide a plurality of cache lines based on a set index of a virtual address, wherein each of the cache lines corresponds to one of a plurality of ways of the set-associative cache; a translation lookaside buffer to provide one of a plurality of way selections based on the set index of the virtual address and a virtual tag of the virtual address, wherein each of the way selections corresponds to one of the ways of the set-associative cache; and a way multiplexer to select one of the cache lines provided by the data cache based on the one of the plurality of way selections.
摘要翻译：具有相应方法和计算机程序的组合关联高速缓存包括：数据高速缓存，用于基于虚拟地址的设置索引提供多条高速缓存行，其中每条高速缓存行对应于设置的多个方式中的一个，关联缓存; 翻译后备缓冲器，用于基于所述虚拟地址的所述设置索引和所述虚拟地址的虚拟标签提供多种方式选择之一，其中所述方式选择中的每一种对应于所述集合关联高速缓存的方式之一; 以及方式多路复用器，用于基于多路选择中的一种选择来选择由数据高速缓存提供的高速缓存行之一。

5. 发明授权

US08918625B1 Speculative scheduling of memory instructions in out-of-order processor based on addressing mode comparison 有权
标题翻译：基于寻址模式比较的乱序处理器中存储器指令的推测调度
公开(公告)号：US08918625B1
公开(公告)日：2014-12-23
申请号：US13297078
申请日：2011-11-15
申请人： R. Frank O'Bleness , Sujat Jamil , Tom Hameenanttila
发明人： R. Frank O'Bleness , Sujat Jamil , Tom Hameenanttila
IPC分类号： G06F9/38 , G06F9/312 , G06F9/30 , G06F9/34
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/34 , G06F9/3838 , G06F9/3842
摘要： A processor that executes instructions out of program order is described. In some implementations, a processor detects whether a second memory operation is dependent on a first memory operation prior to memory address calculation. If the processor detects that the second memory operation is not dependent on the first memory operation, the processor is configured to allow the second memory operation to be scheduled. If the processor detects that the second memory operation is dependent on the first memory operation, the processor is configured to prevent the second memory operation from being scheduled until the first memory operation has been scheduled to reduce the likelihood of having to reexecute the second memory operation.
摘要翻译：描述了以程序顺序执行指令的处理器。在一些实现中，处理器在存储器地址计算之前检测第二存储器操作是否依赖于第一存储器操作。如果处理器检测到第二存储器操作不依赖于第一存储器操作，则处理器被配置为允许调度第二存储器操作。如果处理器检测到第二存储器操作取决于第一存储器操作，则处理器被配置为防止第二存储器操作被调度直到第一存储器操作被调度以减少必须重新执行第二存储器操作的可能性。

6. 发明授权

US08806181B1 Dynamic pipeline reconfiguration including changing a number of stages 有权
标题翻译：动态管道重新配置，包括改变多个阶段
公开(公告)号：US08806181B1
公开(公告)日：2014-08-12
申请号：US12434155
申请日：2009-05-01
申请人： R. Frank O'Bleness , Sujat Jamil , Timothy S. Beatty , Franco Ricci , Tom Hameenanttila , Hong-Yi Chen
发明人： R. Frank O'Bleness , Sujat Jamil , Timothy S. Beatty , Franco Ricci , Tom Hameenanttila , Hong-Yi Chen
IPC分类号： G06F9/38
CPC分类号： G06F9/3873 , G06F9/3869
摘要： According to some embodiments, an apparatus having corresponding methods includes a storage module configured to store data and instructions; a first processor pipeline configured to process the data and instructions when the first processor pipeline is selected; a second processor pipeline configured to process the data and instructions when the second processor pipeline is selected; and a selection module configured to select either the first processor pipeline or the second processor pipeline.
摘要翻译：根据一些实施例，具有相应方法的装置包括被配置为存储数据和指令的存储模块; 配置为当选择所述第一处理器流水线时处理所述数据和指令的第一处理器流水线; 配置为当选择所述第二处理器管线时处理所述数据和指令的第二处理器流水线; 以及选择模块，被配置为选择第一处理器流水线或第二处理器流水线。

7. 发明授权

US09195524B1 Hardware support for performance analysis 有权
标题翻译：硬件支持性能分析
公开(公告)号：US09195524B1
公开(公告)日：2015-11-24
申请号：US13311988
申请日：2011-12-06
申请人： Robert Wiesner , Tom Hameenanttila
发明人： Robert Wiesner , Tom Hameenanttila
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00 , G06F9/54
CPC分类号： G06F11/3648 , G06F9/542 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： Systems, methods, and other embodiments associated with echo cancellation are described. According to one embodiment, an apparatus includes a plurality of first registers configured to respectively store information related to a performance of a processor and a second register in communication with each of the plurality of first registers. The apparatus also includes logic configured to detect a trigger event; and in response to having detected the trigger event, copy the information related to the performance of the processor respectively in the plurality of first registers into the second register.
摘要翻译：描述与回波抵消相关联的系统，方法和其他实施例。根据一个实施例，一种装置包括多个第一寄存器，其被配置为分别存储与处理器的性能相关的信息和与多个第一寄存器中的每一个通信的第二寄存器。该装置还包括配置成检测触发事件的逻辑; 并且响应于检测到所述触发事件，将分别在所述多个第一寄存器中的所述处理器的性能相关的信息复制到所述第二寄存器中。

8. 发明授权

US08458404B1 Programmable cache access protocol to optimize power consumption and performance 有权
标题翻译：可编程缓存访问协议，以优化功耗和性能
公开(公告)号：US08458404B1
公开(公告)日：2013-06-04
申请号：US12540788
申请日：2009-08-13
申请人： Joseph Delgross , Sujat Jamil , R. Frank O'Bleness , Tom Hameenanttila , David E. Miner
发明人： Joseph Delgross , Sujat Jamil , R. Frank O'Bleness , Tom Hameenanttila , David E. Miner
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F2212/502 , G06F2212/601 , Y02D10/13
摘要： A programmable cache and cache access protocol that can be dynamically optimized with respect to either power consumption or performance based on a monitored performance of the cache. A monitoring unit monitors cache misses, load use penalty, and/or other performance parameter, and compares the monitored values against a set of one or more predetermined thresholds. Based on the comparison results, a cache controller configures the programmable cache to operate in a parallel mode, to increase cache performance at the cost of greater power consumption, or in a serial mode, to conserve power at the cost of unnecessary performance. A banked cache memory that supports aligned and unaligned instruction fetches using a banked access strategy, and a cache access controller that includes a prefetch capability are also described.
摘要翻译：可编程高速缓存和缓存访问协议，可根据高速缓存的受监控性能，针对功耗或性能进行动态优化。监视单元监视高速缓存未命中，加载使用罚分和/或其他性能参数，并将所监视的值与一组或多个预定阈值进行比较。基于比较结果，高速缓存控制器将可编程高速缓存器配置为以并行模式操作，以牺牲更大功耗或串行模式为代价来增加高速缓存性能，从而以不必要的性能为代价来节省功耗。还描述了一种使用库存访问策略来支持对齐和未对齐指令取出的存储缓存，并且还描述了包括预取能力的高速缓存访问控制器。

9. 发明授权

US08296525B1 Method and apparatus for data-less bus query 有权
标题翻译：无数据总线查询的方法和装置
公开(公告)号：US08296525B1
公开(公告)日：2012-10-23
申请号：US12537857
申请日：2009-08-07
申请人： Frank O'Bleness , Sujat Jamil , David E. Miner , Tom Hameenanttila , Jeffrey Kehl , Richard Bryant , Kim Schuttenberg
发明人： Frank O'Bleness , Sujat Jamil , David E. Miner , Tom Hameenanttila , Jeffrey Kehl , Richard Bryant , Kim Schuttenberg
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A system and method of tracking multiple non-identification tagged requests in a system with multiple responders using one or more tracking queues. In some embodiments, the system and method may be implemented in a snoop filter covering multiple caches. In some embodiments, a data-less bus query may be used to update the status of a requested line.
摘要翻译：在具有使用一个或多个跟踪队列的多个响应者的系统中跟踪多个非识别标记请求的系统和方法。在一些实施例中，系统和方法可以在覆盖多个高速缓存的窥探过滤器中实现。在一些实施例中，可以使用无数据总线查询来更新所请求行的状态。

10. 发明授权

US08135916B1 Method and apparatus for hardware-configurable multi-policy coherence protocol 有权
标题翻译：用于硬件可配置的多策略一致性协议的方法和装置
公开(公告)号：US08135916B1
公开(公告)日：2012-03-13
申请号：US12416359
申请日：2009-04-01
申请人： R. Frank O'Bleness , Sujat Jamil , David E. Miner , Joseph Delgross , Tom Hameenanttila , Jeffrey Kehl
发明人： R. Frank O'Bleness , Sujat Jamil , David E. Miner , Joseph Delgross , Tom Hameenanttila , Jeffrey Kehl
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/0815 , G06F2212/601
摘要： A processor includes a first level of cache memory and a first set of instructions configured to implement a first cache coherency protocol. The processor also includes a second set of instructions configured to implement a second cache coherency protocol and a cache coherency protocol selector having at least two choice-states. The processor further includes a cache coherency implementer configured to implement the first cache coherency protocol or the second cache coherency with respect to the first level of cache memory based on a selected choice-state of the cache coherency protocol selector.
摘要翻译：处理器包括第一级缓存存储器和被配置为实现第一高速缓存一致性协议的第一组指令。处理器还包括被配置为实现第二高速缓存一致性协议的第二组指令和具有至少两个选择状态的高速缓存一致性协议选择器。处理器还包括缓存一致性实现器，其被配置为基于所选择的高速缓存一致性协议选择器的选择状态来相对于高速缓冲存储器的第一级实现第一高速缓存一致性协议或第二高速缓存一致性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式